公开(公告)号：US20240363385A1

公开(公告)日：2024-10-31

申请号：US18736423

申请日：2024-06-06

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  G11C8/16 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L23/525 ,  H01L25/00 ,  H01L25/065 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B20/20 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40

CPC classification number: H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/3677 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H10B12/05 ,  H10B20/20

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors, first memory cells including at least one second transistor, and overlaying the second metal layer, a third level including third transistors and overlaying the second level, a fourth level including fourth transistors, second memory cells including at least one fourth transistor, and overlaying the third level, where the first level includes memory control circuits which control writing to the second memory cells, and at least one Phase-Lock-Loop (“PLL”) circuit or at least one Digital-Lock-Loop (“DLL”) circuit.

公开(公告)号：US12133389B2

公开(公告)日：2024-10-29

申请号：US17723167

申请日：2022-04-18

Applicant: SK hynix Inc.

Inventor： Sung Wook Jung

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/12 ,  G11C16/28 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/40 ,  G11C16/04 ,  G11C16/08 ,  G11C16/12 ,  G11C16/28 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: A semiconductor memory device includes a memory cell array (MCA) and a pass transistor unit (PTU). The MCA includes memory block(s) that has source selection line(s) (SSL), word lines (WLs), drain selection line(s) (DSL), and dummy WL(s) (DWL). The PTU includes source pass transistor(s) to selectively transmit a source driving signal (source DS) to the SSL, memory pass transistors (MPTs) to selectively transmit a WL DS to the WLs, respectively, drain pass transistor(s) (PT) to selectively transmit a drain DS to the DSL, and dummy PT(s) to selectively transmit a DWL DS to the DWL. The source DS, the WL DS, the drain DS, and the DWL DS may each be associated with a respective voltage range. Sizes of the source PT, the MPTs, the drain PT, and the dummy PTs are set based on the respective voltage ranges.

公开(公告)号：US12112811B2

公开(公告)日：2024-10-08

申请号：US18242397

申请日：2023-09-05

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Ruxin Wei

IPC: G11C5/14 ,  G05F1/46 ,  G05F1/575 ,  G11C16/30 ,  H10B41/41 ,  H10B43/40

CPC classification number: G11C16/30 ,  G05F1/461 ,  G05F1/575 ,  H10B41/41 ,  H10B43/40

Abstract: In certain aspects, a circuit includes an amplifier, a first transistor, a second transistor, a third transistor, a signal pair generation circuit, and a leakage track bias generator circuit connected to the signal pair generation circuit. A gate terminal of the first transistor is connected to an output of the amplifier, and a first terminal of the first transistor is connected to an input of the amplifier. A first terminal of the second transistor is connected to a second terminal of the first transistor. A first terminal of the third transistor is connected to the first terminal of the first transistor, and a second terminal of the third transistor is connected to a second terminal of the second transistor. The signal pair generation circuit is connected to a gate terminal of the second transistor and a gate terminal of the third transistor. The leakage track bias generator circuit includes a resistor, and a first terminal of the resistor is connected to the ground.

公开(公告)号：US20240324231A1

公开(公告)日：2024-09-26

申请号：US18383532

申请日：2023-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUSEONG MIN ,  JAE-BOK BAEK ,  JEEHOON HAN

IPC: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

CPC classification number: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: A semiconductor device includes: a gate electrode on a semiconductor substrate; a gate dielectric pattern between the gate electrode and the semiconductor substrate; a first semiconductor pattern on the semiconductor substrate adjacent to a first side of the gate electrode; and a second semiconductor pattern on the semiconductor substrate adjacent to a second side of the gate electrode, wherein the first semiconductor pattern includes: a first via part in contact with the semiconductor substrate; and a first plate part on the first via part, wherein the second semiconductor pattern includes: a second via part in contact with the semiconductor substrate; and a second plate part on the second via part, wherein each of the first and second plate parts extends lengthwise in a direction parallel to a top surface of the semiconductor substrate.

公开(公告)号：US12101932B2

公开(公告)日：2024-09-24

申请号：US17450729

申请日：2021-10-13

Applicant: Micron Technology, Inc.

Inventor： Erwin E. Yu ,  Surendranath C. Eruvuru ,  Yoshiaki Fukuzumi ,  Tomoko Ogura Iwasaki

IPC: H10B41/41 ,  B81B7/02 ,  G11C7/10 ,  G11C16/24 ,  H10B41/20 ,  H10B43/20 ,  H10B43/40

CPC classification number: H10B41/41 ,  B81B7/02 ,  G11C7/1012 ,  G11C16/24 ,  H10B41/20 ,  H10B43/20 ,  H10B43/40 ,  B81B2201/07

Abstract: A microelectronic device comprises a stack structure, first digit lines, second digit lines, and multiplexer devices. The stack structure comprises an access line region comprising a lower group of conductive structures, and a select gate region overlying the access line region and comprising an upper group of conductive structures. The first digit lines are coupled to strings of memory cells, and the second digit lines are coupled to additional strings of memory cells. The second digit lines are horizontally offset from the first digit lines in a first direction and are substantially horizontally aligned with the first digit lines in a second direction. The multiplexer devices are coupled to page buffer devices, the first digit lines, and the second digit lines. The multiplexer devices comprise transistors in electrical communication with the upper group of conductive structures. Additional microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US12100651B2

公开(公告)日：2024-09-24

申请号：US17680914

申请日：2022-02-25

Applicant: SK hynix Inc.

Inventor： Nam Jae Lee

IPC: H10B43/27 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L23/5226 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor memory device, and a method of manufacturing a semiconductor memory device, includes a stacked structure including a plurality of conductive layers for local lines stacked on a semiconductor substrate defined by a cell region and a slimming region to be spaced apart from each other, wherein the plurality of conductive layers for local lines are stacked in a step structure in the slimming region. The semiconductor memory device also includes a plurality of contact plugs formed to penetrate the stack structure in the slimming region, the plurality of contact plugs corresponding to each of the conductive layers for local lines. Each of the plurality of contact plugs includes a protrusion part protruding horizontally, and the protrusion part is connected to a corresponding conductive layer for local lines among the plurality of conductive layers for local lines.

公开(公告)号：US12096622B2

公开(公告)日：2024-09-17

申请号：US17502140

申请日：2021-10-15

Applicant: Applied Materials, Inc.

Inventor： Armin Saeedi Vahdat ,  John Hautala ,  Johannes M. van Meer

IPC: H10B41/20 ,  B82Y10/00 ,  B82Y40/00 ,  H10B41/23 ,  H10B41/27 ,  H10B41/41 ,  H10B43/20 ,  H10B43/23 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B41/20 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  B82Y10/00 ,  B82Y40/00

Abstract: A semiconductor manufacturing process and semiconductor device having an airgap to isolate bottom implant portions of a substrate from upper source and drain device structure to reduce bottom current leakage and parasitic capacitance with an improved scalability on n-to-p spacing scaling. The disclosed device can be implanted to fabricate nanosheet FET and other such semiconductor device. The airgap is formed by etching into the substrate, below a trench in a vertical and horizontal direction. The trench is then filled with dielectric and upper device structure formed on either side of the dielectric filler trench.

公开(公告)号：US20240306394A1

公开(公告)日：2024-09-12

申请号：US18434356

申请日：2024-02-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungun Lee ,  Pansuk Kwak ,  Changyeon Yu

IPC: H10B43/40 ,  G11C16/08 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

CPC classification number: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  G11C16/08

Abstract: A memory device includes a stack structure, in which a common source line is formed, and a peripheral circuit structure overlapping the stack structure when viewed in plan view and comprising a common source line driver configured to discharge the common source line. The common source line driver includes a first common source line driving unit, electrically connected to the common source line through a first network and configured to discharge the common source line, and a second common source line driving unit electrically connected to the common source line through a second network, different from the first network, and configured to discharge the common source line. The first common source line driving unit and the second common source line driving unit are controlled independently of each other.

公开(公告)号：US12089407B2

公开(公告)日：2024-09-10

申请号：US17574740

申请日：2022-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghoon Kwon ,  Chungki Min

IPC: H10B43/27 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A semiconductor device includes a peripheral circuit structure including a lower substrate, a plurality of circuits formed on the lower substrate, and a plurality of wiring layers connected to the plurality of circuits, an upper substrate covering the peripheral circuit structure and including a through opening, a memory stack structure including a plurality of gate lines, a memory cell contact passing through at least one of the plurality of gate lines to contact one gate line from among the plurality of gate lines, the memory cell contact extending to the peripheral circuit structure through the through opening and being configured to be electrically connected to a first wiring layer from among the plurality of wiring layers, and a plurality of dummy channel structures passing through at least one of the plurality of gate lines to extend to the peripheral circuit structure through the through opening.

公开(公告)号：US12087753B2

公开(公告)日：2024-09-10

申请号：US18479431

申请日：2023-10-02

Applicant: SK hynix Inc.

Inventor： Nam Jae Lee

IPC: H01L25/18 ,  G11C16/08 ,  G11C16/24 ,  H01L23/00 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L25/18 ,  G11C16/08 ,  G11C16/24 ,  H01L24/20 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H01L2924/1431 ,  H01L2924/1438

Abstract: A semiconductor device includes: a substrate extending in a first direction and a second direction intersecting with the first direction; a plurality of input/output pads disposed at one side of the substrate; a first circuit adjacent to the input/output pads in the first direction; a second circuit disposed to be spaced farther apart from the input/output pads in the first direction than the first circuit; a first memory cell array overlapping the first circuit; a second memory cell array overlapping the second circuit; first metal source patterns overlapping the first memory cell array and being spaced apart from each other in the second direction; and a second metal source pattern overlapping the second memory cell array and formed to have a width wider than a width of each of the first metal source patterns in the second direction.