公开(公告)号：US20230343698A1

公开(公告)日：2023-10-26

申请号：US17883073

申请日：2022-08-08

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Jaemyung CHOI ,  Tae Sun KIM ,  Janggeun LEE ,  Kang-ill SEO

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76834 ,  H01L21/76832 ,  H01L21/76807 ,  H01L23/53295

Abstract: Provided is a semiconductor device including at least one front-end-of-line (FEOL) element connected to an interconnect structure, the interconnect structure including: a 1st metal pattern or via structure with a spacer structure on a sidewall thereof; and a 1st interlayer dielectric (ILD) layer formed at sides of the 1st metal pattern or via structure with the spacer structure on the sidewall thereof, wherein the spacer structure includes a dielectric material different from a material included in the 1st ILD layer.

公开(公告)号：US20230343697A1

公开(公告)日：2023-10-26

申请号：US17841245

申请日：2022-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Janggeun LEE ,  Jaemyung CHOI ,  Kang-ill SEO

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877

Abstract: A connection structure for an integrated circuit includes: a 1st layer including a 1st metal line; a 2nd layer, above the 1st layer, including a 1st via; and a 3rd layer, above the 2nd layer, including a 2nd metal line connected to the 1st metal line through the 1st via, wherein the 1st via comprises a spacer structure at a side of an upper portion of the 1st via, the spacer structure comprising an insulation material.

公开(公告)号：US20230253327A1

公开(公告)日：2023-08-10

申请号：US17735768

申请日：2022-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Janggeun LEE ,  Kang-ill SEO

IPC: H01L23/535 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L23/5226 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76895

Abstract: A connection structure of an integrated circuit may include: a top via in a 1st layer; and a super via on the top via, the super via being connected to the top via, wherein the super via penetrates through a 2nd layer, on the 1st layer, and a 3rd layer on the 2nd layer, and each of the 2nd layer and the 3rd layer is provided for formation of at least one metal pattern or at least one via therein.

公开(公告)号：US20250022797A1

公开(公告)日：2025-01-16

申请号：US18378789

申请日：2023-10-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaemyung CHOI ,  Janggeun LEE ,  Wonhyuk HONG ,  Kang-ill SEO

IPC: H01L23/528 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor device includes: a frontside structure including at least one of a front-end-of-line (FEOL) structure, a middle-of-line (MOL) structure, and a back-end-of-line (BEOL) structure; a 1st metal line on the frontside structure; and a 2nd metal line on the frontside structure, wherein the 1st metal line has a greater width than the 2nd metal line in a same direction, and the 1st metal line and the 2nd metal line have an equal height.