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公开(公告)号:US20240249110A1
公开(公告)日:2024-07-25
申请号:US18344201
申请日:2023-06-29
Applicant: Samsung Electronics Co., Ltd.
Inventor: Minje KIM , Soon-Wan KWON , Wooseok YI , Jangho AN
IPC: G06N3/04
CPC classification number: G06N3/04
Abstract: A device includes: an operation module configured to store and operate a weight for an operation of a layer of a neural network model; a control module configured to generate setting information for performing the operation of the layer by the neural network model using the stored weight; an input module configured to receive input data for the operation of the layer based on the generated setting information; a merging module configured to receive operation results of the operation of the layer from the operation module and merge the received operation results of the layer; a post-processing module configured to receive the merged operation results of the layer from the merging module and post-process the received merged operation results of the layer; and an output stream module configured to convert and store the post-processed operation results based on the generated setting information.
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公开(公告)号:US20240112004A1
公开(公告)日:2024-04-04
申请号:US18115891
申请日:2023-03-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jangho AN , Seungchul JUNG , Soon-Wan KWON
CPC classification number: G06N3/063 , G06F7/5443 , G06N3/04 , H10B10/12 , H10B10/18
Abstract: An apparatus including a memory layer including a plurality of front-end-of-line (FEOL) memory cells and a logic layer including plural arithmetic logic gates including back-end-of-line (BEOL) transistors, the plurality of BEOL transistors being vertically stacked on respective upper ends of the plurality of memory cells, wherein each of multiple transistors of the plurality of BEOL transistors operates as a multiplier and is configured to provide an operation result with respect to first values stored in corresponding memory cells of the plurality of memory cells.
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