中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

16 records (took 0.015 seconds)

    APPARATUS AND METHOD WITH NEURAL NETWORK OPERATIONS
    2.
    发明申请
    APPARATUS AND METHOD WITH NEURAL NETWORK OPERATIONS 有权

    公开(公告)号：US20220343147A1

    公开(公告)日：2022-10-27

    申请号：US17408951

    申请日：2021-08-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Soon-Wan KWON ,  Minje KIM ,  Sang Joon KIM

    IPC: G06N3/063 ,  G06N3/04 ,  G06F7/501 ,  G06F17/16 ,  H03M1/12

    Abstract: A neural network apparatus includes: a first processing circuit and a second processing circuit each configured to perform a vector-by-matrix multiplication (VMM) operation on a weight and an input activation; a first register configured to store an output of the first processing circuit; an adder configured to add an output of the first register and an output of the second processing circuit; a second register configured to store an output of the adder; and an input circuit configured to input a same input activation to the first processing circuit and the second processing circuit and control the first processing circuit and the second processing circuit.

    METHOD AND MEMORY DEVICE WITH IN-MEMORY COMPUTING
    4.
    发明公开
    METHOD AND MEMORY DEVICE WITH IN-MEMORY COMPUTING 审中-公开

    公开(公告)号：US20240241694A1

    公开(公告)日：2024-07-18

    申请号：US18355046

    申请日：2023-07-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Daekun YOON ,  Soon-Wan KWON ,  Seok Ju YUN ,  Jaehyuk LEE ,  Dong-Jin CHANG

    IPC: G06F7/544 ,  G06F7/501 ,  G11C7/10

    CPC classification number: G06F7/5443 ,  G06F7/501 ,  G11C7/1012

    Abstract: Disclosed is an in-memory computing device and method. The in-memory computing device includes: a memory unit including bit cells configured to store first input data having a reference-bit-count, receive second input data also having the reference-bit-count, and perform a multiplication operation between the first input data and the second input data; and an operation unit including: a first adder tree configured to output intermediate operation results by adding results of performing the multiplication operation output with respect to each of the bit cells; a branch module configured to branch the intermediate operation results according to an operation mode of the in-memory computing device; and a second adder tree configured to output a final operation result based on an output of the branch module.

    ELECTRONIC DEVICE AND METHOD WITH DATA SCALING
    5.
    发明公开
    ELECTRONIC DEVICE AND METHOD WITH DATA SCALING 审中-公开

    公开(公告)号：US20240241691A1

    公开(公告)日：2024-07-18

    申请号：US18524520

    申请日：2023-11-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Chang-Woo SHIN ,  Soon-Wan KWON ,  Seijoon KIM ,  Hyunsoo KIM ,  Seungkeun YOON

    IPC: G06F5/01

    CPC classification number: G06F5/01

    Abstract: An electronic device and method with data scaling is provided herein. The electronic device may include a computing device that includes an analog computing circuit, where the computing device may scale an input of the analog computing circuit using a first scaling factor and/or scale a weight of the analog computing circuit using a second scaling factor, where the input includes a plurality of input values within a preset input maximum range of values of the computing device, and the weight includes a plurality of weight values within a preset weight maximum range of values of the computing device, and rescale an output of the analog computing circuit based on the first scaling factor and/or the second scaling factor. The first and second scaling factors may respectively scale values of the input and the weight to exceed respective preset maximum ranges of values.

    DEVICE AND METHOD WITH COMPUTATIONAL MEMORY
    6.
    发明公开
    DEVICE AND METHOD WITH COMPUTATIONAL MEMORY 审中-公开

    公开(公告)号：US20240112708A1

    公开(公告)日：2024-04-04

    申请号：US18108737

    申请日：2023-02-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyungwoo LEE ,  Soon-Wan KWON ,  Seungchul JUNG

    IPC: G11C7/10 ,  G06F7/544 ,  G11C7/12 ,  G11C11/54

    CPC classification number: G11C7/1084 ,  G06F7/5443 ,  G11C7/12 ,  G11C11/54

    Abstract: A computational memory device and a method using the computational memory device are provided. The computational memory device includes memory banks configured to store weight data of a neural network model and a weight memory block configured to provide at least some of the weight data from memory banks in response to a weight request, a computational memory block physically stacked on the weight memory block such faces of the respective blocks face each other, the computational memory block configured to perform a multiply-accumulate (MAC) operation between the at least some of the weight data and at least some of input data by using a bit cell array including bit cells, and a communication interface configured to perform communication between the weight memory block and the computational memory block.

    IN-MEMORY COMPUTING (IMC) PROCESSOR AND OPERATING METHOD OF IMC PROCESSOR
    7.
    发明公开
    IN-MEMORY COMPUTING (IMC) PROCESSOR AND OPERATING METHOD OF IMC PROCESSOR 审中-公开

    公开(公告)号：US20240061649A1

    公开(公告)日：2024-02-22

    申请号：US18306686

    申请日：2023-04-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Soon-Wan KWON ,  Seok Ju YUN ,  Seungchul JUNG

    IPC: G06F7/544 ,  G06F7/527 ,  G11C7/10

    CPC classification number: G06F7/5443 ,  G06F7/5277 ,  G11C7/1069

    Abstract: An in-memory computing (IMC) processor includes IMC macros, and includes a static random access memory (SRAM) IMC device including the plurality of IMC macros, and configured to perform a multiply and accumulate (MAC) operation between input data and first weight data of a first weight map applied to a first of IMC macros in a first direction in which an input feature map including the input data is written to the first IMC macro, and a two-dimensional (2D) shift accumulator configured to perform a shift operation on partial sums corresponding to respective MAC operation results of the IMC macros and accumulate a result of the shift operation.

Patent Agency Ranking