公开(公告)号：US10109645B2

公开(公告)日：2018-10-23

申请号：US15786864

申请日：2017-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changseop Yoon ,  Junggun You ,  YoungJoon Park ,  Jeonghyo Lee

IPC: H01L21/70 ,  H01L21/336 ,  H01L27/118 ,  H01L29/423 ,  H01L29/66 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06

Abstract: A semiconductor device includes a first device isolation layer defining active regions spaced apart from each other along a first direction on a substrate, second device isolation layers defining a plurality of active patterns protruding from the substrate, the second device isolation layers extending in the first direction to be spaced apart from each other in a second direction and connected to the first device isolation layer, a gate structure extending in the second direction on the first device isolation layer between the active regions, a top surface of the second device isolation layer being lower than a top surface of the active pattern, a top surface of the first device isolation layer being higher than the top surface of the active pattern, and at least part of a bottom surface of the gate structure being higher than the top surface of the active pattern.

公开(公告)号：US09799674B2

公开(公告)日：2017-10-24

申请号：US15050607

申请日：2016-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changseop Yoon ,  Junggun You ,  YoungJoon Park ,  Jeonghyo Lee

IPC: H01L21/70 ,  H01L21/336 ,  H01L27/118 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/7846 ,  H01L21/76224 ,  H01L27/11807 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/66659

Abstract: A semiconductor device includes a first device isolation layer defining active regions spaced apart from each other along a first direction on a substrate, second device isolation layers defining a plurality of active patterns protruding from the substrate, the second device isolation layers extending in the first direction to be spaced apart from each other in a second direction and connected to the first device isolation layer, a gate structure extending in the second direction on the first device isolation layer between the active regions, a top surface of the second device isolation layer being lower than a top surface of the active pattern, a top surface of the first device isolation layer being higher than the top surface of the active pattern, and at least part of a bottom surface of the gate structure being higher than the top surface of the active pattern.