公开(公告)号：US20230403010A1

公开(公告)日：2023-12-14

申请号：US18175795

申请日：2023-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunyoon Cho ,  Eunseok Shin ,  Youngdon Choi ,  Jaeduk Han ,  Hyuntae Kim ,  Jeonghyu Yang ,  Sanghun Lee

IPC: H03K19/096 ,  H03K5/15

CPC classification number: H03K19/096 ,  H03K5/15013

Abstract: A parallel-to-serial converter includes first to fourth input nodes configured to receive first to fourth data input signals, respectively, and an output node configured to output a data output signal. First to fourth logic circuits are provided, which are configured to electrically couple respective ones of the first to fourth input nodes one-at-a-time to the output node, in synchronization with first to fourth clock signals. The first logic circuit includes a first input circuit, a second input circuit, and an output circuit electrically coupled to the first and second input circuits. The output circuit includes a first pull-up transistor and a first pull-down transistor having drain terminals coupled to the output node, a second pull-up transistor connected between a source terminal of the first pull-up transistor and a first power supply node, and a second pull-down transistor connected between a source terminal of the first pull-down transistor and a second power supply node.