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    Signal generator with multiple outputs
    3.
    发明授权
    Signal generator with multiple outputs 有权

    公开(公告)号：US10063220B2

    公开(公告)日：2018-08-28

    申请号：US15004829

    申请日：2016-01-22

    申请人： METROTECH CORPORATION

    发明人： George Mainescu ,  Ion Dracea ,  Razvan Gabriel Stefanoiu ,  Paul Lucian Lacatus

    IPC分类号： H03K5/15 ,  H03K17/00 ,  G01V13/00

    CPC分类号： H03K5/15013 ,  G01V3/081 ,  G01V13/00 ,  H03K17/007

    摘要： A signal generator that provides signals for multiple outputs is presented. In some embodiments, a signal generator can include switching circuitry that is coupled to provide a signal to an active output of a plurality of outputs in response to control signals; a driver that provides the signal to the switching circuitry, the signal being at a frequency appropriate for the active output; and a logic that provides the control signals to the switching circuitry and provides a waveform to the driver, the waveform having the frequency appropriate for the active output, the control signals indicating which of the plurality of outputs is the active output.

    Device for correcting multi-phase clock signal
    4.
    发明授权
    Device for correcting multi-phase clock signal 有权

    公开(公告)号：US10038433B2

    公开(公告)日：2018-07-31

    申请号：US15468025

    申请日：2017-03-23

    申请人： SK Hynix Inc. ,  Korea University Research and Business Foundation

    发明人： Jeong Cho ,  Soowon Kim ,  Jinhoon Hyun ,  Chanhui Jeong ,  Daehan Kwon

    IPC分类号： H03K3/017 ,  H03K5/04 ,  H03K7/08 ,  H03K5/156 ,  H03K5/15

    CPC分类号： H03K5/1565 ,  H03K5/15013

    摘要： A device for correcting a multi-phase clock signal includes a first duty ratio adjusting circuit (DRAC) to adjust a duty ratio of a first clock signal; a variable delay line (VDL) delaying a second clock signal; a second DRAC adjusting a duty ratio of the VDL output; first and second differential clock generating circuits (DFCGs) generating differential signals from first and second DRAC outputs, respectively; an edge combining circuit combining edges of outputs from the DFCGs; a duty ratio detecting circuit (DRDC) detecting a duty ratio of a first DRAC output or a first DFCG output in a first mode and of an edge combining circuit output in a second mode; a first control circuit controlling the first and second DRACs using a DRDC output in the first mode; and a second control circuit controlling the VDL using the DRDC output in the second mode.

    Clock generator and method of adjusting phases of multiphase clocks by the same
    6.
    发明授权
    Clock generator and method of adjusting phases of multiphase clocks by the same 有权

    公开(公告)号：US09768759B2

    公开(公告)日：2017-09-19

    申请号：US14971100

    申请日：2015-12-16

    申请人： MegaChips Corporation

    发明人： Izuho Tanihira

    IPC分类号： H03K3/00 ,  H03K5/15 ,  H03K3/03

    CPC分类号： H03K5/15013 ,  H03K3/0315 ,  H03K5/15026

    摘要： A clock generator that outputs multiphase clocks comprises a ring oscillator that includes a plurality of inverter circuits connected in a circular pattern and outputs, from the inverter circuits, clocks provided with a delay time based on a delay control signal, a first frequency divider that divides an injection clock by a first value and outputs the clock as a reference clock, a second frequency divider that divides one of the multiphase clocks by a second value and outputs the clock as a comparison clock, and a frequency comparator that compares frequencies of the reference clock and the comparison clock and output the delay control signal based on a result of the comparison. The ring oscillator is configured to adjust the delay time based on the delay control signal.

    Tunable clock system
    8.
    发明授权
    Tunable clock system 有权
    可调时钟系统

    公开(公告)号：US09124256B2

    公开(公告)日：2015-09-01

    申请号：US14589444

    申请日：2015-01-05

    申请人： Laurence H. Cooke

    发明人： Laurence H. Cooke

    IPC分类号： H03K3/00 ,  H03K5/13 ,  H03K5/00

    CPC分类号： H03K5/15 ,  H03K5/131 ,  H03K5/133 ,  H03K5/15013 ,  H03K2005/00065 ,  H03K2005/00247

    摘要： A memory-like structure composed of variable resistor elements for use in tuning respective branches and leaves of a clock distribution structure, which may be used to compensate for chip-by-chip and/or combinatorial logic path-by-path delay variations, which may be due, for example, to physical variations in deep submicron devices and interconnections, is presented. A single system clocked scan flip-flop with the capability to perform delay test measurements is also presented. Methods for measuring combinatorial logic path delays to determine the maximum clock frequency and delays to program the variable resistors, as well as methods for calibrating and measuring the programmed variable resistors, are also presented.

    摘要翻译： 由可变电阻器元件组成的存储器状结构，用于调整时钟分配结构的相应分支和叶片，其可用于补偿逐芯片和/或组合逻辑逐个路径延迟变化，其中 可能是因为例如深亚微米器件和互连中的物理变化。 还提供了具有执行延迟测试测量功能的单个系统时钟扫描触发器。 还提出了用于测量组合逻辑路径延迟以确定最大时钟频率和编程可变电阻器的延迟的方法，以及用于校准和测量编程的可变电阻器的方法。

    TUNABLE CLOCK SYSTEM
    9.
    发明申请
    TUNABLE CLOCK SYSTEM 审中-公开
    时钟系统

    公开(公告)号：US20150109039A1

    公开(公告)日：2015-04-23

    申请号：US14589444

    申请日：2015-01-05

    申请人： Laurence H. COOKE

    发明人： Laurence H. COOKE

    IPC分类号： H03K5/13

    CPC分类号： H03K5/15 ,  H03K5/131 ,  H03K5/133 ,  H03K5/15013 ,  H03K2005/00065 ,  H03K2005/00247

    摘要： A memory-like structure composed of variable resistor elements for use in tuning respective branches and leaves of a clock distribution structure, which may be used to compensate for chip-by-chip and/or combinatorial logic path-by-path delay variations, which may be due, for example, to physical variations in deep submicron devices and interconnections, is presented. A single system clocked scan flip-flop with the capability to perform delay test measurements is also presented. Methods for measuring combinatorial logic path delays to determine the maximum clock frequency and delays to program the variable resistors, as well as methods for calibrating and measuring the programmed variable resistors, are also presented.

    摘要翻译： 由可变电阻器元件组成的存储器状结构，用于调整时钟分配结构的相应分支和叶片，其可用于补偿逐芯片和/或组合逻辑逐个路径延迟变化，其中 可能是因为例如深亚微米器件和互连中的物理变化。 还提供了具有执行延迟测试测量功能的单个系统时钟扫描触发器。 还提出了用于测量组合逻辑路径延迟以确定最大时钟频率和编程可变电阻器的延迟的方法，以及用于校准和测量编程的可变电阻器的方法。

    Clock generator and method thereof
    10.
    发明授权
    Clock generator and method thereof 有权
    时钟发生器及其方法

    公开(公告)号：US08963603B2

    公开(公告)日：2015-02-24

    申请号：US14245515

    申请日：2014-04-04

    申请人： Realtek Semiconductor Corp.

    发明人： Shih-Hsiun Huang ,  Shian-Ru Lin

    IPC分类号： G06F1/04 ,  H03K3/86

    CPC分类号： H03K3/86 ,  H03K5/15013

    摘要： A clock generation device includes a first delay unit, a frequency divider, an angle delay unit and a first calculating unit. The first delay unit receives an input clock and delays the input clock by a first preset period to generate an input delay clock. The frequency divider divides a frequency of the delay clock to generate a first frequency-divided clock and a second frequency-divided clock. A frequency of each of the first frequency-divided clock and the second frequency-divided clock is a preset multiple of the input delay clock. The angle delay unit delays the first frequency-divided clock by a second preset period to generate a first delay clock. The first calculating unit determines a trigger time of a first edge of a first output clock with reference to voltage levels of the first frequency-divided clock and the first delay clock and determines a falling time of a second edge of the first output clock with reference to voltage levels of the input clock and the first delay clock.

    摘要翻译： 时钟发生装置包括第一延迟单元，分频器，角度延迟单元和第一计算单元。 第一延迟单元接收输入时钟并将输入时钟延迟第一预设周期以产生输入延迟时钟。 分频器分频延迟时钟的频率以产生第一分频时钟和第二分频时钟。 第一分频时钟和第二分频时钟中的每一个的频率是输入延迟时钟的预设倍数。 角度延迟单元将第一分频时钟延迟第二预设周期以产生第一延迟时钟。 第一计算单元参考第一分频时钟和第一延迟时钟的电压电平来确定第一输出时钟的第一边沿的触发时间，并且以参考的方式确定第一输出时钟的第二边缘的下降时间 到输入时钟和第一延迟时钟的电压电平。