公开(公告)号：US20220085064A1

公开(公告)日：2022-03-17

申请号：US17225493

申请日：2021-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jesuk MOON ,  Juyoung LIM ,  Jongsoo KIM ,  Sunil SHIM ,  Haemin LEE ,  Wonseok CHO

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11565 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/1157

Abstract: A vertical memory device includes a gate electrode structure on a substrate, a channel extending through the gate electrode structure, and an etch stop layer on a sidewall of the gate electrode structure. The gate electrode structure includes gate electrodes spaced apart from each other in a first direction and stacked in a staircase shape. The channel includes a first portion and a second portion contacting the first portion. A lower surface of the second portion has a width less than a width of an upper surface of the first portion. The etch stop layer contacts at least one gate electrode of the gate electrodes, and overlaps an upper portion of the first portion of the channel in a horizontal direction. The at least one gate electrode contacting the etch stop layer is a dummy gate electrode including an insulating material.

公开(公告)号：US20210399008A1

公开(公告)日：2021-12-23

申请号：US17154159

申请日：2021-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Young LIM ,  Jongsoo KIM ,  Jesuk MOON ,  Dongwoo KIM ,  Sunil SHIM ,  Wonseok CHO

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11573 ,  H01L27/11526

Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region, an electrode structure including electrodes vertically stacked on the substrate, the electrodes including pad portions on the connection region, respectively, and the pad portions of the electrodes being stacked in a staircase structure, first vertical structures penetrating the electrode structure on the cell array region, and second vertical structures penetrating the electrode structure on the connection region, each of the second vertical structures including first parts spaced apart from each other in a first direction, and at least one second part connecting the first parts to each other, the at least one second part penetrating sidewalls of the pad portions, respectively.

公开(公告)号：US20210013304A1

公开(公告)日：2021-01-14

申请号：US16701427

申请日：2019-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojoon RYU ,  Kiyoon KANG ,  Seogoo KANG ,  Shinhwan KANG ,  Jesuk MOON ,  Byunggon PARK ,  Jaeryong SIM ,  Jinsoo LIM ,  Jisung CHEON ,  Jeehoon HAN

IPC: H01L29/06 ,  H01L23/31 ,  G11C5/06 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A semiconductor device including a substrate having a cell, peripheral, and boundary area; a stack structure on the cell area and including insulating and interconnection layers that are alternately stacked; a molding layer on the peripheral area boundary areas; a selection line isolation pattern extending into the stack structure; a cell channel structure passing through the stack structure; and first dummy patterns extending into the molding layer on the peripheral area, wherein upper surfaces of the first dummy patterns, an upper surface of the selection line isolation pattern, and an upper surface of the cell channel structure are coplanar, and at least one of the first dummy patterns extends in parallel with the selection line isolation pattern or cell channel structure from upper surfaces of the first dummy patterns, the upper surface of the selection line isolation pattern, and the upper surface of the cell channel structure toward the substrate.