公开(公告)号：US11651201B2

公开(公告)日：2023-05-16

申请号：US16522920

申请日：2019-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan-Kyung Kim ,  Soon-Young Kim ,  Jin-Min Kim ,  Jae-Hong Min ,  Sang-Kil Lee ,  Young-Nam Hwang

IPC: G11C16/08 ,  G06N3/063 ,  G06F9/30 ,  G06F7/544

CPC classification number: G06N3/063 ,  G06F7/5443 ,  G06F9/30105 ,  G11C16/08

Abstract: Provided is a memory device that includes a memory bank including a plurality of memory cells arranged in a region where a plurality of word lines and a plurality of bit lines of the memory device intersect each other, a sense amplifier configured to amplify a signal transmitted through selected bit lines among the plurality of bit lines, and an arithmetic circuit configured to receive a first operand from the sense amplifier, receive a second operand from outside the memory device, and perform an arithmetic operation by using the first operand and the second operand, based on an internal arithmetic control signal generated in the memory device.

公开(公告)号：US20200160157A1

公开(公告)日：2020-05-21

申请号：US16522920

申请日：2019-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHAN-KYUNG KIM ,  Soon-Young Kim ,  Jin-Min Kim ,  Jae-Hong Min ,  Sang-Kil Lee ,  Young-Nam Hwang

IPC: G06N3/063 ,  G06F7/544 ,  G11C16/08 ,  G06F9/30

Abstract: Provided is a memory device that includes a memory bank including a plurality of memory cells arranged in a region where a plurality of word lines and a plurality of bit lines of the memory device intersect each other, a sense amplifier configured to amplify a signal transmitted through selected bit lines among the plurality of bit lines, and an arithmetic circuit configured to receive a first operand from the sense amplifier, receive a second operand from outside the memory device, and perform an arithmetic operation by using the first operand and the second operand, based on an internal arithmetic control signal generated in the memory device.