公开(公告)号：US20140346617A1

公开(公告)日：2014-11-27

申请号：US14228806

申请日：2014-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Pil KIM ,  Yun-Young YEOH

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/4966 ,  H01L29/66545

Abstract: A semiconductor device includes an interlayer insulating film on a substrate, the interlayer insulating film including first and second trenches, a gate insulating film in the first and second trenches, a first conductivity type work function control film on the gate insulating film in the first trench, a second conductivity type work function control film on the gate insulating film in the second trench, a first gate metal on the first conductivity type work function control film, the first gate metal filling the first trench, a second gate metal on the gate insulating film in the second trench, and a carrier mobility improving film on the second conductivity type work function control film, the carrier mobility improving film filling the second trench.

Abstract translation: 半导体器件包括在基板上的层间绝缘膜，所述层间绝缘膜包括第一沟槽和第二沟槽，第一沟槽和第二沟槽中的栅极绝缘膜，第一沟槽中的栅极绝缘膜上的第一导电型功函数控制膜 在第二沟槽中的栅极绝缘膜上形成第二导电型功函数控制膜，第一导电型功函数控制膜上的第一栅极金属，填充第一沟槽的第一栅极金属，绝缘栅上的第二栅极金属 第二沟槽中的膜，以及第二导电型功函数控制膜上的载流子迁移率改善膜，填充第二沟槽的载流子迁移率改善膜。

公开(公告)号：US20130316514A1

公开(公告)日：2013-11-28

申请号：US13956482

申请日：2013-08-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Pil KIM ,  Young-Goan JANG ,  Dong-Won KIM ,  Hag-Ju CHO

IPC: H01L21/28 ,  H01L21/76

CPC classification number: H01L21/28008 ,  H01L21/28123 ,  H01L21/76 ,  H01L21/76232 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

Abstract: A method of fabricating a gate includes sequentially forming an insulation layer and a conductive layer on substantially an entire surface of a substrate. The substrate has a device isolation layer therein and a top surface of the device isolation layer is higher than a top surface of the substrate. The method includes planarizing a top surface of the conductive layer and forming a gate electrode by patterning the insulation layer and the conductive layer.

Abstract translation: 制造栅极的方法包括在基板的基本上整个表面上依次形成绝缘层和导电层。 衬底在其中具有器件隔离层，器件隔离层的顶表面高于衬底的顶表面。 该方法包括通过图案化绝缘层和导电层来平坦化导电层的顶表面并形成栅电极。