公开(公告)号：US20200286818A1

公开(公告)日：2020-09-10

申请号：US16723455

申请日：2019-12-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghyun Cho ,  Youngsik Hur ,  Youngkwan Lee ,  Jongrok Kim

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package includes: an interposer substrate including a core substrate and a connection structure, the core substrate having a cavity and having through-vias connecting upper and lower surfaces thereof, and the connection structure including an insulating member on the upper surface and a redistribution layer on the insulating member; a semiconductor chip on an upper surface of the connection structure and including connection pads connected to the redistribution layer; a passive component accommodated in the cavity; a first insulating layer disposed between the core substrate and the connection structure; a first wiring layer on the first insulating layer and connecting the through-vias and the passive component to the redistribution layer; a second insulating layer on the lower surface of the core substrate; and a second wiring layer on a lower surface of the second insulating layer and connected to the through-vias.

公开(公告)号：US11626362B2

公开(公告)日：2023-04-11

申请号：US17333615

申请日：2021-05-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghyun Cho ,  Youngsik Hur ,  Youngkwan Lee ,  Jongrok Kim

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A method of manufacturing a semiconductor package includes preparing a core substrate having an upper surface and a lower surface, and including a cavity. A passive component is disposed in the cavity. A first insulating layer is formed on the upper surface of the core substrate and in the cavity and encapsulates the passive component. Through-vias are formed that penetrate the core substrate and the first insulating layer, and a first wiring layer is formed on the first insulating layer. The first wiring layer connects the through-vias and the passive component. A connection structure including an insulating member is formed on the first insulating layer and a redistribution layer is formed in the insulating member. The redistribution layer is connected to the first wiring layer. A semiconductor chip is disposed on an upper surface of the connection structure. The semiconductor chip has connection pads connected to the redistribution layer.

公开(公告)号：US20210296222A1

公开(公告)日：2021-09-23

申请号：US17333615

申请日：2021-05-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghyun CHO ,  Youngsik Hur ,  Youngkwan Lee ,  Jongrok Kim

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A method of manufacturing a semiconductor package includes preparing a core substrate having an upper surface and a lower surface, and including a cavity. A passive component is disposed in the cavity. A first insulating layer is formed on the upper surface of the core substrate and in the cavity and encapsulates the passive component. Through-vias are formed that penetrate the core substrate and the first insulating layer, and a first wiring layer is formed on the first insulating layer. The first wiring layer connects the through-vias and the passive component. A connection structure including an insulating member is formed on the first insulating layer and a redistribution layer is formed in the insulating member. The redistribution layer is connected to the first wiring layer. A semiconductor chip is disposed on an upper surface of the connection structure. The semiconductor chip has connection pads connected to the redistribution layer.

公开(公告)号：US11031328B2

公开(公告)日：2021-06-08

申请号：US16723455

申请日：2019-12-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghyun Cho ,  Youngsik Hur ,  Youngkwan Lee ,  Jongrok Kim

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes: an interposer substrate including a core substrate and a connection structure, the core substrate having a cavity and having through-vias connecting upper and lower surfaces thereof, and the connection structure including an insulating member on the upper surface and a redistribution layer on the insulating member; a semiconductor chip on an upper surface of the connection structure and including connection pads connected to the redistribution layer; a passive component accommodated in the cavity; a first insulating layer disposed between the core substrate and the connection structure; a first wiring layer on the first insulating layer and connecting the through-vias and the passive component to the redistribution layer; a second insulating layer on the lower surface of the core substrate; and a second wiring layer on a lower surface of the second insulating layer and connected to the through-vias.

公开(公告)号：US20200219833A1

公开(公告)日：2020-07-09

申请号：US16704217

申请日：2019-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngkwan LEE ,  Youngsik HUR ,  Junghyun Cho ,  Taehee Han ,  Jongrok Kim

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package may include: a connection structure including an insulating member having a first surface having a recess portion and a second surface opposing the first surface, a plurality of first pads disposed on a bottom surface of the recess portion, a plurality of second pads embedded in the second surface of the insulating member, and a redistribution layer disposed between the plurality of first pads and the plurality of second pads and connected to the plurality of first and second pads; a semiconductor chip disposed on the first surface of the insulating member and having a plurality of connection electrodes electrically connected, respectively, to the plurality of first pads; and a passivation layer disposed on the second surface of the insulating member and having a plurality of openings exposing, respectively, the plurality of second pads.