公开(公告)号：US11031328B2

公开(公告)日：2021-06-08

申请号：US16723455

申请日：2019-12-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghyun Cho ,  Youngsik Hur ,  Youngkwan Lee ,  Jongrok Kim

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes: an interposer substrate including a core substrate and a connection structure, the core substrate having a cavity and having through-vias connecting upper and lower surfaces thereof, and the connection structure including an insulating member on the upper surface and a redistribution layer on the insulating member; a semiconductor chip on an upper surface of the connection structure and including connection pads connected to the redistribution layer; a passive component accommodated in the cavity; a first insulating layer disposed between the core substrate and the connection structure; a first wiring layer on the first insulating layer and connecting the through-vias and the passive component to the redistribution layer; a second insulating layer on the lower surface of the core substrate; and a second wiring layer on a lower surface of the second insulating layer and connected to the through-vias.

公开(公告)号：US11469148B2

公开(公告)日：2022-10-11

申请号：US16681341

申请日：2019-11-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngkwan Lee ,  Youngsik Hur ,  Taehee Han ,  Yonghoon Kim ,  Yuntae Lee

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes: a frame having a cavity and including a wiring structure connecting first and second surfaces of the frame; a first connection structure on the first surface of the frame and including a first redistribution layer connected to the wiring structure; a first semiconductor chip on the first connection structure within the cavity; an encapsulant encapsulating the first semiconductor chip and covering the second surface of the frame; a second connection structure including a second redistribution layer including a first redistribution pattern and first connection vias; and a second semiconductor chip disposed on the second connection structure and having connection pads connected to the second redistribution layer.

公开(公告)号：US20200286818A1

公开(公告)日：2020-09-10

申请号：US16723455

申请日：2019-12-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghyun Cho ,  Youngsik Hur ,  Youngkwan Lee ,  Jongrok Kim

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package includes: an interposer substrate including a core substrate and a connection structure, the core substrate having a cavity and having through-vias connecting upper and lower surfaces thereof, and the connection structure including an insulating member on the upper surface and a redistribution layer on the insulating member; a semiconductor chip on an upper surface of the connection structure and including connection pads connected to the redistribution layer; a passive component accommodated in the cavity; a first insulating layer disposed between the core substrate and the connection structure; a first wiring layer on the first insulating layer and connecting the through-vias and the passive component to the redistribution layer; a second insulating layer on the lower surface of the core substrate; and a second wiring layer on a lower surface of the second insulating layer and connected to the through-vias.

公开(公告)号：US11626362B2

公开(公告)日：2023-04-11

申请号：US17333615

申请日：2021-05-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghyun Cho ,  Youngsik Hur ,  Youngkwan Lee ,  Jongrok Kim

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A method of manufacturing a semiconductor package includes preparing a core substrate having an upper surface and a lower surface, and including a cavity. A passive component is disposed in the cavity. A first insulating layer is formed on the upper surface of the core substrate and in the cavity and encapsulates the passive component. Through-vias are formed that penetrate the core substrate and the first insulating layer, and a first wiring layer is formed on the first insulating layer. The first wiring layer connects the through-vias and the passive component. A connection structure including an insulating member is formed on the first insulating layer and a redistribution layer is formed in the insulating member. The redistribution layer is connected to the first wiring layer. A semiconductor chip is disposed on an upper surface of the connection structure. The semiconductor chip has connection pads connected to the redistribution layer.

公开(公告)号：US11239148B2

公开(公告)日：2022-02-01

申请号：US16684808

申请日：2019-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngkwan Lee ,  Youngsik Hur ,  Taehee Han

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/552

Abstract: A semiconductor package includes a core layer formed of a ferromagnetic material, and includes a frame passing through the core layer and having a through-hole, a semiconductor chip disposed in the through-hole of the frame, and having an active surface on which a connection pad is disposed, and an inactive surface opposite to the active surface, an encapsulant covering at least a portion of the semiconductor chip, and a first connection structure including a first redistribution layer disposed on the active surface of the semiconductor chip and electrically connected to the connection pad.

公开(公告)号：US20210296222A1

公开(公告)日：2021-09-23

申请号：US17333615

申请日：2021-05-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghyun CHO ,  Youngsik Hur ,  Youngkwan Lee ,  Jongrok Kim

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A method of manufacturing a semiconductor package includes preparing a core substrate having an upper surface and a lower surface, and including a cavity. A passive component is disposed in the cavity. A first insulating layer is formed on the upper surface of the core substrate and in the cavity and encapsulates the passive component. Through-vias are formed that penetrate the core substrate and the first insulating layer, and a first wiring layer is formed on the first insulating layer. The first wiring layer connects the through-vias and the passive component. A connection structure including an insulating member is formed on the first insulating layer and a redistribution layer is formed in the insulating member. The redistribution layer is connected to the first wiring layer. A semiconductor chip is disposed on an upper surface of the connection structure. The semiconductor chip has connection pads connected to the redistribution layer.

公开(公告)号：US20200168518A1

公开(公告)日：2020-05-28

申请号：US16681341

申请日：2019-11-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngkwan LEE ,  Youngsik Hur ,  Taehee Han ,  Yonghoon Kim ,  Yuntae Lee

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes: a frame having a cavity and including a wiring structure connecting first and second surfaces of the frame; a first connection structure on the first surface of the frame and including a first redistribution layer connected to the wiring structure; a first semiconductor chip on the first connection structure within the cavity; an encapsulant encapsulating the first semiconductor chip and covering the second surface of the frame; a second connection structure including a second redistribution layer including a first redistribution pattern and first connection vias; and a second semiconductor chip disposed on the second connection structure and having connection pads connected to the second redistribution layer.

公开(公告)号：US11257770B2

公开(公告)日：2022-02-22

申请号：US16679916

申请日：2019-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonwook So ,  Youngsik Hur ,  Yongho Baek ,  Jungchul Gong ,  Dooil Kim

IPC: H01L23/66 ,  A61B5/021 ,  H01L23/00 ,  H01L23/528 ,  H01L23/495

Abstract: A biological information detecting apparatus includes: an LC resonant pressure sensor including a resonant circuit including a capacitor and an inductor, and having a resonant frequency that changes depending on a change in external pressure applied to the capacitor; and an integrated circuit (IC) chip package including a coil type antenna radiating a radio frequency (RF) signal within a preset frequency band, wherein a change in the resonant frequency results in a change in a power transmission rate depending on a inductive coupling between the resonant frequency and a frequency of the RF signal. The IC chip package includes the coil type antenna disposed in a region overlapping the LC resonant pressure sensor in a plan view of the IC chip package.