公开(公告)号：US20240146312A1

公开(公告)日：2024-05-02

申请号：US18480817

申请日：2023-10-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wooseok CHOI ,  Joonghyun SONG

IPC: H03L7/081 ,  H03K5/00

CPC classification number: H03L7/0812 ,  H03K5/00006 ,  H03K2005/00019

Abstract: A frequency multiplier includes a first digitally controlled delay line (DCDL) configured to receive a first clock signal and generate a second clock signal by changing a phase of the first clock signal, a multiplying delay-locked loop (MDLL) configured to generate a third clock signal by multiplying a frequency of the second clock signal, and a DCDL calibration circuit configured to receive the second clock signal and generate a gain signal for adjusting a gain of the first DCDL where a difference between a maximum delay and a minimum delay of the first DCDL is substantially equal to a period of the third clock signal.