公开(公告)号：US20250119326A1

公开(公告)日：2025-04-10

申请号：US18906291

申请日：2024-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeongjin Oh ,  Junghoon Chun ,  Minsu Park

IPC: H04L25/49 ,  H02M1/088

Abstract: A transmitter includes a driver including an edge driver that is configured to output a first signal and a fourth signal based on a selection drive signal and a middle driver that is configured to output a second signal and a third signal, a body bias circuit configured to provide the body bias voltage to the middle driver based on a body bias control signal, a control circuit configured to provide the selection drive signal to the driver and to transmit the body bias control signal to the body bias circuit, based on a first comparison result or a second comparison result, and a comparator configured to provide the first comparison result of comparing a level of the second signal with a second level and to provide the second comparison result of comparing a level of the third signal with a third level.

公开(公告)号：US11552833B2

公开(公告)日：2023-01-10

申请号：US17376637

申请日：2021-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaekwon Kim ,  Junghoon Chun

IPC: H04L25/49 ,  H04L27/06 ,  H04L25/03

Abstract: A receiver includes an interface configured to receive a data signal based on an n-level pulse amplitude modulation (PAM-n) in which n is an integer equal to or greater than 4. The interface may include an analog-digital converting circuit configured to adjust a reference voltage, for distinguishing second bit data from the data signal in a second section, based on first bit data converted from the data signal in a first section and the first bit data converted from the data signal in the second section, the second section being after the first section.

公开(公告)号：US12126474B2

公开(公告)日：2024-10-22

申请号：US18094852

申请日：2023-01-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaekwon Kim ,  Junghoon Chun

IPC: H04L25/03 ,  H04L25/49 ,  H04L27/06

CPC classification number: H04L25/4917 ,  H04L25/03057 ,  H04L27/06

Abstract: A receiver includes an interface configured to receive a data signal based on an n-level pulse amplitude modulation (PAM-n) in which n is an integer equal to or greater than 4. The interface may include an analog-digital converting circuit configured to adjust a reference voltage, for distinguishing second bit data from the data signal in a second section, based on first bit data converted from the data signal in a first section and the first bit data converted from the data signal in the second section, the second section being after the first section.

公开(公告)号：US11711245B2

公开(公告)日：2023-07-25

申请号：US17243683

申请日：2021-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngseob Suh ,  Byungwook Cho ,  Donghyuk Lim ,  Junghoon Chun

IPC: H04L25/03

CPC classification number: H04L25/03178 ,  H04L25/03057

Abstract: An apparatus includes an equalization circuit, an error prediction circuit, a sequence estimation circuit, and a selection circuit. The equalization circuit is configured to generate a first data sequence and a first equalized signal from an input signal received through a channel. The error prediction circuit is configured to predict an error based on the first equalized signal when the error is predicted. When the error is predicted, the sequence estimation circuit is configured to generate a second data sequence from the first data sequence and the predicted error. The selection circuit is configured to output the second data sequence when the predicted error is determined to be an actual error and to otherwise output the first data sequence.

公开(公告)号：US20220086028A1

公开(公告)日：2022-03-17

申请号：US17243683

申请日：2021-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngseob Suh ,  Byungwook Cho ,  Donghyuk Lim ,  Junghoon Chun

IPC: H04L25/03

Abstract: An apparatus includes an equalization circuit, an error prediction circuit, a sequence estimation circuit, and a selection circuit. The equalization circuit is configured to generate a first data sequence and a first equalized signal from an input signal received through a channel. The error prediction circuit is configured to predict an error based on the first equalized signal when the error is predicted. When the error is predicted, the sequence estimation circuit is configured to generate a second data sequence from the first data sequence and the predicted error. The selection circuit is configured to output the second data sequence when the predicted error is determined to be an actual error and to otherwise output the first data sequence.