公开(公告)号：US20150076324A1

公开(公告)日：2015-03-19

申请号：US14488637

申请日：2014-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： EUN-YOUNG JIN ,  KYO-JIN CHOO ,  YU-JIN PARK ,  HAN-KOOK CHO

IPC: H04N5/378 ,  H03L7/00

CPC classification number: H04N5/378 ,  H04N5/3355

Abstract: An integrated circuit comprises a first signal transfer block comprising first through (M)-th aligning blocks that are cascade-coupled to produce first aligned control signals through (M)-th aligned control signals, respectively, by aligning first control signals with a clock signal, wherein M is an integer greater than one, and a functional block divided into first through (M)-th sub-functional blocks configured to perform a same function in parallel, each of the first through (M)-th sub-functional blocks operating according to corresponding ones of the first aligned control signals through (M)-th aligned control signals generated by the first through (M)-th aligning blocks.

Abstract translation: 集成电路包括第一信号传输块，其包括通过（M）第一对准块级联耦合以分别通过（M）对准的控制信号产生第一对准的控制信号，通过将第一控制信号与时钟 信号，其中M是大于1的整数，以及分配成并行执行相同功能的第一至第（M）个子功能块的功能块，第一至第（M）个子功能 根据由第一到第（M）个对准块产生的（M）对准的控制信号，根据第一对准的控制信号中的相应的一个控制信号进行操作。