METHOD AND APPARATUS FOR PROCESSING SHUFFLE INSTRUCTION
    2.
    发明申请
    METHOD AND APPARATUS FOR PROCESSING SHUFFLE INSTRUCTION 有权
    用于处理小巧指示的方法和装置

    公开(公告)号:US20150127924A1

    公开(公告)日:2015-05-07

    申请号:US14330562

    申请日:2014-07-14

    Abstract: A method and corresponding apparatus for processing a shuffle instruction are provided. Shuffle units are configured in a hierarchical structure, and each of the shuffle units generates a shuffled data element array by performing shuffling on an input data element array. In the hierarchical structure, which includes an upper shuffle unit and a lower shuffle unit, the shuffled data element array output from the lower shuffle unit is input to the upper shuffle unit as a portion of the input data element array for the upper shuffle unit.

    Abstract translation: 提供了一种用于处理洗牌指令的方法和相应的装置。 洗牌单元以分层结构配置,并且每个洗牌单元通过在输入数据元素阵列上执行洗牌来生成洗牌数据元素阵列。 在包括上部混洗单元和下部混洗单元的层次结构中,从下部混洗单元输出的混洗数据单元阵列作为上部随机播放单元的输入数据单元阵列的一部分输入到上部混洗单元。

    METHOD OF SCHEDULING LOOPS FOR PROCESSOR HAVING A PLURALITY OF FUNCTIONAL UNITS
    3.
    发明申请
    METHOD OF SCHEDULING LOOPS FOR PROCESSOR HAVING A PLURALITY OF FUNCTIONAL UNITS 有权
    具有多个功能单元的处理器的调度方法

    公开(公告)号:US20150149747A1

    公开(公告)日:2015-05-28

    申请号:US14330675

    申请日:2014-07-14

    Abstract: Provided is a loop scheduling method including scheduling a first loop using execution units, and scheduling a second loop using execution units available as a result of the scheduling of the first loop. An n-th loop (n>2) may be scheduled using a result of scheduling an (n−1)-th loop, similar to the (n−1)-th loop. The first loop may be a higher priority loop than the second loop.

    Abstract translation: 提供了一种循环调度方法,包括使用执行单元调度第一循环,并且使用作为第一循环的调度的结果可用的执行单元来调度第二循环。 可以使用类似于第(n-1)个循环的调度第(n-1)个循环的结果来调度第n个循环(n> 2)。 第一个循环可以是比第二个循环更高的优先级循环。

    PROCESSOR USING MINI-CORES
    4.
    发明申请
    PROCESSOR USING MINI-CORES 审中-公开
    加工商使用MINI CORES

    公开(公告)号:US20150012723A1

    公开(公告)日:2015-01-08

    申请号:US14324302

    申请日:2014-07-07

    Abstract: A mini-core and a processor using such a mini-core are provided in which functional units of the mini-core are divided into a scalar domain processor and a vector domain processor. The processor includes at least one such mini-core, and all or a portion of functional units from among the functional units of the mini-core operate based on an operation mode.

    Abstract translation: 提供了一种使用这种微型核心的微型核心和处理器,其中小型核心的功能单元被划分为标量域处理器和向量域处理器。 处理器包括至少一个这样的微型核心,并且来自小型核心的功能单元中的功能单元的全部或一部分基于操作模式进行操作。

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