公开(公告)号：US20250056799A1

公开(公告)日：2025-02-13

申请号：US18596764

申请日：2024-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kumhyo Kang ,  Hongsoo Kim ,  Jeon Il Lee ,  Hyun-Mook Choi

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A semiconductor memory device, and a semiconductor package and an electronic system including the same are provided. The semiconductor memory device includes a substrate including a plurality of mat regions and a mat separation region between ones of the mat regions, a peripheral circuit structure on the substrate and including peripheral circuits, a cell array structure on the peripheral circuit structure, a first through-via extending into the substrate in the mat separation region, and a second through-via extending into the cell array structure on the mat separation region and electrically connected to the first through-via, wherein the second through-via overlaps the first through-via.

公开(公告)号：US20250089280A1

公开(公告)日：2025-03-13

申请号：US18809515

申请日：2024-08-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ingyu Baek ,  Kumhyo Kang ,  Hyunmook Choi ,  Soonhyung Hong

IPC: H01G4/30

Abstract: An example semiconductor device includes a capacitor structure on a substrate. The capacitor structure includes a first electrode structure, a second electrode structure, and a capacitor dielectric layer. The first electrode structure includes first horizontal electrode portions apart from each other in a first direction perpendicular to the substrate and a first conductive pillar connected to each of the first horizontal electrode portions and extending in the first direction. The second electrode structure includes a second conductive pillar extending through the first horizontal electrode portions in the first direction and second horizontal electrode portions apart from each other in the first direction on a side wall of the second conductive pillar and alternately arranged with the first horizontal electrode portions. The capacitor dielectric layer is between the side wall of the second conductive pillar and the first horizontal electrode portions.