公开(公告)号：US20250046754A1

公开(公告)日：2025-02-06

申请号：US18664499

申请日：2024-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Mook Choi ,  Keum Hyo Kang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/42 ,  H01L23/48 ,  H01L23/538 ,  H10B80/00

Abstract: A semiconductor package includes a package substrate including a trench; a first chip structure including a first buffer chip and a plurality of first semiconductor chips on the first buffer chip; and a second chip structure including a second buffer chip and a second semiconductor chip on the second buffer chip, wherein one of the first and second chip structures is on the trench, the other one of the first and second chip structures is on a top surface of the package substrate, a first physical layer (PHY) region of the first buffer chip overlaps with a second PHY region of the second buffer chip in a direction perpendicular to the top surface of the package substrate.

公开(公告)号：US20250056799A1

公开(公告)日：2025-02-13

申请号：US18596764

申请日：2024-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kumhyo Kang ,  Hongsoo Kim ,  Jeon Il Lee ,  Hyun-Mook Choi

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A semiconductor memory device, and a semiconductor package and an electronic system including the same are provided. The semiconductor memory device includes a substrate including a plurality of mat regions and a mat separation region between ones of the mat regions, a peripheral circuit structure on the substrate and including peripheral circuits, a cell array structure on the peripheral circuit structure, a first through-via extending into the substrate in the mat separation region, and a second through-via extending into the cell array structure on the mat separation region and electrically connected to the first through-via, wherein the second through-via overlaps the first through-via.

公开(公告)号：US20240357831A1

公开(公告)日：2024-10-24

申请号：US18532504

申请日：2023-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seryeun Yang ,  Jeon Il Lee ,  Hyeran Lee ,  Hyun-Mook Choi

IPC: H10B53/20 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H10B51/10 ,  H10B51/20 ,  H10B53/10

CPC classification number: H10B53/20 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/10 ,  H10B51/20 ,  H10B53/10

Abstract: A semiconductor device may include a substrate; semiconductor patterns that are stacked on the substrate, extend in a first direction parallel to a top surface of the substrate, and are spaced apart from each other; a gate electrode including horizontal portions, that extend in a second direction crossing the first direction, and a vertical portion, that is in contact with the horizontal portions and extends in a third direction perpendicular to the top surface of the substrate; a gate dielectric layer between the semiconductor patterns and the gate electrode; and a ferroelectric layer between the gate dielectric layer and the gate electrode. Each of the semiconductor patterns may include impurity regions and a channel region between the impurity regions, the vertical portion may be on a first side surface of the channel region, and the horizontal portions may be on a top and bottom surface of the channel region.