公开(公告)号：US20230081723A1

公开(公告)日：2023-03-16

申请号：US17804742

申请日：2022-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JU HYUNG LEE ,  DONG UK KWON ,  SUN CHUL KIM ,  YONG HYUN KIM ,  MIN JAE LEE

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538

Abstract: A method of fabricating a semiconductor package includes disposing a preliminary semiconductor package on a stage, the preliminary semiconductor package including a substrate to which a pad part is attached, an interposer disposed on the substrate, and a semiconductor chip disposed between the substrate and the interposer. A bonding tool is disposed on the interposer. The bonding tool includes a first region and a second region outside of the first region. The second region of the bonding tool corresponds to the pad part. The interposer and the substrate are bonded to each other.

公开(公告)号：US20220157845A1

公开(公告)日：2022-05-19

申请号：US17443448

申请日：2021-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MIN JAE LEE ,  Jin Do Byun ,  Young-Hoon Son ,  Young Don Choi ,  Pan Suk Kwak ,  Myung Hun Lee ,  Jung Hwan Choi

IPC: H01L27/11573 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  G11C16/08

Abstract: A non-volatile memory chip comprises a cell region that includes a first surface, a second surface opposite to the first surface, a first cell structure, and a second cell structure spaced apart from the first cell structure; a peripheral circuit region on the first surface of the cell region, and that includes a first peripheral circuit connected to the first cell structure, a second peripheral circuit connected to the second cell structure, and a connection circuit between the first and second peripheral circuits; a through via between the first and second cell structures and that extends from the second surface of the cell region to the connection circuit of the peripheral circuit region; a redistribution layer that covers the through via on the second surface of the cell region, is connected to the through via, and extends along the second surface; and a chip pad connected to the redistribution layer.