公开(公告)号：US12111680B2

公开(公告)日：2024-10-08

申请号：US17871374

申请日：2022-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae Hyun Kwon ,  Min-Hyeong Kim ,  Wang Soo Kim

IPC: G06F1/08 ,  H04L25/03

CPC classification number: G06F1/08 ,  H04L25/03057

Abstract: A memory device including a receiving circuit is provided. The receiving circuit of the memory device includes a first path receiving a received signal and outputting the received signal directly as a first corrected signal in a current clock signal, a second path holding or tracking the received signal and outputting a second corrected signal in the current clock signal, wherein the second corrected signal is held in a previous clock signal, a summing circuit summing the first corrected signal and the second corrected signal and outputting a summed received signal, and a decision feedback equalizer comparing the summed received signal with a reference signal to decide equalized data and outputting the equalized data in the current clock signal.