公开(公告)号：US20220319907A1

公开(公告)日：2022-10-06

申请号：US17537571

申请日：2021-11-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoungwoo LEE ,  Minkwon CHOI

IPC: H01L21/762 ,  H01L29/66 ,  H01L21/311 ,  H01L21/308

Abstract: Disclosed is a semiconductor device fabrication method including forming an interlayer dielectric layer and a lower mask layer on a substrate, forming on the lower mask layer first and second upper mask patterns spaced apart from each other in a first direction, wherein each of the first and second upper mask patterns has a line part extending in a second direction and a first protruding part protruding from the line part, forming a spacer covering sidewalls of the line parts of the first and second upper mask patterns and a filling pattern filling a space between the first protruding parts of the first and second upper mask patterns, etching the lower mask layer to form lower mask patterns, etching the interlayer dielectric layer to form grooves on the interlayer dielectric layer, and forming wiring lines in the grooves.