-
公开(公告)号:US20150143312A1
公开(公告)日:2015-05-21
申请号:US14449377
申请日:2014-08-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Joong-Won JEON , Ji-Youn SONG , Mun-Su SHIN , Seong-Yul PARK , Suk-Joo LEE
IPC: G06F17/50
CPC classification number: G03F1/36 , G03F1/70 , G03F7/70433
Abstract: A method of designing patterns of semiconductor devices includes forming a plurality of tiles having patterns on a wafer, measuring the patterns of the plurality of tiles, analyzing the measurements of the patterns and determining a tile having such a size that the measurements linearly vary according to a design size and pattern density, and modifying the pattern density of the determined tile.
Abstract translation: 一种设计半导体器件图形的方法包括:在晶片上形成具有图案的多个瓦片,测量多个瓦片的图案,分析图案的测量结果,以及确定具有这样的尺寸的瓦片,使得测量值根据 设计尺寸和图案密度,以及修改确定的瓷砖的图案密度。