公开(公告)号：US11563004B2

公开(公告)日：2023-01-24

申请号：US16789588

申请日：2020-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myoung-Sun Lee ,  Keun Hwi Cho

IPC: H01L27/092 ,  H01L27/02 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L21/02 ,  H01L29/417

Abstract: There is provided a semiconductor device having enhanced operation performance by utilizing a cut region where a gate cut is implemented. There is provided a semiconductor device comprising a first active pattern, a second active pattern, a third active pattern, and a fourth active pattern, all of which extend in parallel in a first direction, and are arranged along a second direction intersecting the first direction; a first gate electrode extended in the second direction on the first to fourth active patterns a first cut region extended in the first direction between the first active pattern and the second active pattern to cut the first gate electrode and a second cut region extended in the first direction between the third active pattern and the fourth active pattern to cut the first gate electrode, wherein one or more first dimensional features related to the first cut region is different from one or more second dimensional features related to the second cut region.

公开(公告)号：US11908867B2

公开(公告)日：2024-02-20

申请号：US18157591

申请日：2023-01-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myoung-Sun Lee ,  Keun Hwi Cho

IPC: H01L27/092 ,  H01L27/02 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L21/02 ,  H01L29/417

CPC classification number: H01L27/0924 ,  H01L27/0207 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/7848

Abstract: There is provided a semiconductor device having enhanced operation performance by utilizing a cut region where a gate cut is implemented. There is provided a semiconductor device comprising a first active pattern, a second active pattern, a third active pattern, and a fourth active pattern, all of which extend in parallel in a first direction, and are arranged along a second direction intersecting the first direction; a first gate electrode extended in the second direction on the first to fourth active patterns a first cut region extended in the first direction between the first active pattern and the second active pattern to cut the first gate electrode and a second cut region extended in the first direction between the third active pattern and the fourth active pattern to cut the first gate electrode, wherein one or more first dimensional features related to the first cut region is different from one or more second dimensional features related to the second cut region.

公开(公告)号：US20230139574A1

公开(公告)日：2023-05-04

申请号：US17851289

申请日：2022-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNGGUN YOU ,  Beomjin Park ,  Sughyun Sung ,  Hojin Lee ,  Dongwon Kim ,  Donggyu Lee ,  Myoung-Sun Lee ,  Keun Hwi Cho ,  Hanbyul Choi ,  Jiyong Ha

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: A semiconductor device includes: an active pattern on a substrate, wherein the active pattern includes a plurality of channel layers stacked on one another; a plurality of source/drain patterns spaced apart from each other in a first direction and disposed on the active pattern, wherein the plurality of source/drain patterns are connected to each other through the plurality of channel layers; and first and second gate electrodes at least partially surrounding the channel layers and extending in a second direction, wherein the second direction intersects the first direction, wherein the active pattern has a first sidewall and a second sidewall that faces the first sidewall, and wherein a first distance between the first sidewall of the active pattern and an outer sidewall of the first gate electrode is different from a second distance between the second sidewall of the active pattern and an outer sidewall of the second gate electrode.

公开(公告)号：US12237391B2

公开(公告)日：2025-02-25

申请号：US17851289

申请日：2022-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggun You ,  Beomjin Park ,  Sughyun Sung ,  Hojin Lee ,  Dongwon Kim ,  Donggyu Lee ,  Myoung-Sun Lee ,  Keun Hwi Cho ,  Hanbyul Choi ,  Jiyong Ha

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes: an active pattern on a substrate, wherein the active pattern includes a plurality of channel layers stacked on one another; a plurality of source/drain patterns spaced apart from each other in a first direction and disposed on the active pattern, wherein the plurality of source/drain patterns are connected to each other through the plurality of channel layers; and first and second gate electrodes at least partially surrounding the channel layers and extending in a second direction, wherein the second direction intersects the first direction, wherein the active pattern has a first sidewall and a second sidewall that faces the first sidewall, and wherein a first distance between the first sidewall of the active pattern and an outer sidewall of the first gate electrode is different from a second distance between the second sidewall of the active pattern and an outer sidewall of the second gate electrode.

公开(公告)号：US20230163131A1

公开(公告)日：2023-05-25

申请号：US18157591

申请日：2023-01-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myoung-Sun Lee ,  Keun Hwi Cho

IPC: H01L27/092 ,  H01L27/02

CPC classification number: H01L27/0924 ,  H01L27/0207 ,  H01L21/823814

Abstract: There is provided a semiconductor device having enhanced operation performance by utilizing a cut region where a gate cut is implemented. There is provided a semiconductor device comprising a first active pattern, a second active pattern, a third active pattern, and a fourth active pattern, all of which extend in parallel in a first direction, and are arranged along a second direction intersecting the first direction; a first gate electrode extended in the second direction on the first to fourth active patterns a first cut region extended in the first direction between the first active pattern and the second active pattern to cut the first gate electrode and a second cut region extended in the first direction between the third active pattern and the fourth active pattern to cut the first gate electrode, wherein one or more first dimensional features related to the first cut region is different from one or more second dimensional features related to the second cut region.