公开(公告)号：US20160125931A1

公开(公告)日：2016-05-05

申请号：US14827686

申请日：2015-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUYEON DOO ,  TAEYOUNG OH ,  NAMJONG KIM ,  CHULSUNG PARK

IPC: G11C11/406 ,  G11C11/4076

CPC classification number: G11C11/40626 ,  G11C11/406

Abstract: A semiconductor memory device includes a memory circuit including a plurality of memory cells and a refresh control circuit. The refresh control circuit is configured to determine a number of times to perform a target row refresh (TRR) in response to a mode register set (MRS) code signal, wherein the MRS code signal is generated in response to a temperature change, and the refresh control circuit is configured to maintain a refresh cycle of at least two of the memory cells for a period of time when the refresh cycle is changed due to the temperature change.

Abstract translation: 一种半导体存储器件包括包括多个存储单元和刷新控制电路的存储器电路。 刷新控制电路被配置为响应于模式寄存器组（MRS）代码信号来确定执行目标行刷新（TRR）的次数，其中响应于温度变化而产生MRS代码信号，并且 刷新控制电路被配置为在由于温度变化而改变刷新周期的一段时间内保持至少两个存储单元的刷新周期。