公开(公告)号：US20200020380A1

公开(公告)日：2020-01-16

申请号：US16579994

申请日：2019-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGJUN SHIN ,  SU YEON DOO ,  TAEYOUNG OH

IPC: G11C11/4076 ,  G11C8/18 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/408

Abstract: A semiconductor memory device includes a command decoder configured to generate an auto-sync signal in response to a command for writing data at a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to phase synchronize a second clock, having a clock frequency higher than a clock frequency of a first clock, with the first clock in response to the auto-sync signal.

公开(公告)号：US20170004869A1

公开(公告)日：2017-01-05

申请号：US15081071

申请日：2016-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGJUN SHIN ,  SU YEON DOO ,  TAEYOUNG OH

IPC: G11C11/4076 ,  G11C11/4096 ,  G11C29/52 ,  G11C11/408

CPC classification number: G11C11/4076 ,  G11C7/1045 ,  G11C8/18 ,  G11C11/4087 ,  G11C11/4096

Abstract: A semiconductor memory device includes a command decoder configured to generate an auto-sync signal in response to a command for writing data at a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to phase synchronize a second clock, having a clock frequency higher than a clock frequency of a first clock, with the first clock in response to the auto-sync signal.

Abstract translation: 半导体存储器件包括命令解码器，其被配置为响应于在存储器单元写入数据或从存储器单元读取数据的命令产生自动同步信号，以及内部数据时钟产生电路，被配置为将第二时钟 具有高于第一时钟的时钟频率的时钟频率，其中第一时钟响应于自动同步信号。

公开(公告)号：US20210057016A1

公开(公告)日：2021-02-25

申请号：US17093786

申请日：2020-11-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGJUN SHIN ,  SU YEON DOO ,  TAEYOUNG OH

IPC: G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C7/10 ,  G11C8/18

Abstract: A semiconductor memory device includes a command decoder configured to generate an auto-sync signal in response to a command for writing data at a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to phase synchronize a second clock, having a clock frequency higher than a clock frequency of a first clock, with the first clock in response to the auto-sync signal.

公开(公告)号：US20200286544A1

公开(公告)日：2020-09-10

申请号：US16879829

申请日：2020-05-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGJUN SHIN ,  SU YEON DOO ,  TAEYOUNG OH

IPC: G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C7/10 ,  G11C8/18

Abstract: A semiconductor memory device includes a command decoder configured to generate an auto-sync signal in response to a command for writing data at a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to phase synchronize a second clock, having a clock frequency higher than a clock frequency of a first clock, with the first clock in response to the auto-sync signal.

公开(公告)号：US20230343386A1

公开(公告)日：2023-10-26

申请号：US18154945

申请日：2023-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： TAEYOUNG OH

IPC: G11C11/4093 ,  G11C7/10 ,  H03K19/0175 ,  G11C11/4076 ,  H10B80/00 ,  H01L23/48

CPC classification number: G11C11/4093 ,  G11C7/109 ,  G11C7/1051 ,  H03K19/0175 ,  G11C11/4076 ,  H10B80/00 ,  H01L23/481

Abstract: A semiconductor die includes a first pin configured to output a first on-die termination (ODT) control signal to a second semiconductor die, the second semiconductor die comprising a plurality of second ODT circuits each having an ODT that is responsive to the first ODT control signal; and a second pin configured to receive a second ODT control signal output from the second semiconductor die, the semiconductor die comprising a plurality of first ODT circuits each having an ODT that is responsive to the second ODT control signal.

公开(公告)号：US20230315297A1

公开(公告)日：2023-10-05

申请号：US18295087

申请日：2023-04-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： TAEYOUNG OH

IPC: G06F3/06 ,  G11C11/4076

CPC classification number: G06F3/0611 ,  G11C11/4076 ,  G06F3/0655 ,  G06F3/0679

Abstract: A memory system that controls latency for a plurality of clock signals and outputs at least one of read data and write data includes a memory controller configured to receive a data output command from a host, generate a plurality of clock signals for outputting data, and control latency of the plurality of clock signals, and an input/output (I/O) circuit configured to output data based on the clock signals having the controlled latency.

公开(公告)号：US20210343328A1

公开(公告)日：2021-11-04

申请号：US17376915

申请日：2021-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGJUN SHIN ,  SU YEON DOO ,  TAEYOUNG OH

IPC: G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C7/10 ,  G11C8/18

Abstract: A semiconductor memory device includes a command decoder configured to generate an auto-sync signal in response to a command for writing data at a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to phase synchronize a second clock, having a clock frequency higher than a clock frequency of a first clock, with the first clock in response to the auto-sync signal.

公开(公告)号：US20250037757A1

公开(公告)日：2025-01-30

申请号：US18914640

申请日：2024-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： TAEYOUNG OH

IPC: G11C11/4093 ,  G11C7/10 ,  G11C11/4076 ,  H01L23/48 ,  H03K19/0175 ,  H10B80/00

Abstract: A semiconductor die includes a first pin configured to output a first on-die termination (ODT) control signal to a second semiconductor die, the second semiconductor die comprising a plurality of second ODT circuits each having an ODT that is responsive to the first ODT control signal; and a second pin configured to receive a second ODT control signal output from the second semiconductor die, the semiconductor die comprising a plurality of first ODT circuits each having an ODT that is responsive to the second ODT control signal.

公开(公告)号：US20240290371A1

公开(公告)日：2024-08-29

申请号：US18499444

申请日：2023-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNGDO UM ,  TAEYOUNG OH ,  HYE-RAN KIM

IPC: G11C11/4076 ,  G06F1/08 ,  G06F1/12 ,  G06F12/02 ,  H03K5/13 ,  H03K5/156

CPC classification number: G11C11/4076 ,  G06F1/08 ,  G06F1/12 ,  G06F12/023 ,  H03K5/13 ,  H03K5/1565

Abstract: A memory device includes a divide circuit configured to generate an internal data clock signal based on a data clock signal, wherein the data clock signal has a first voltage level for a first time period and toggles during a second time period consecutive to the first time period, a detect circuit configured to generate a feedback data corresponding to the first voltage level based on the internal data clock signal, and an input/output circuit configured to output the feedback data to an external device.

公开(公告)号：US20190180809A1

公开(公告)日：2019-06-13

申请号：US16278339

申请日：2019-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGJUN SHIN ,  SU YEON DOO ,  TAEYOUNG OH

IPC: G11C11/4076 ,  G11C8/18 ,  G11C11/408 ,  G11C11/4096 ,  G11C7/10

CPC classification number: G11C11/4076 ,  G11C7/1045 ,  G11C8/18 ,  G11C11/4087 ,  G11C11/4096

Abstract: A semiconductor memory device includes a command decoder configured to generate an auto-sync signal in response to a command for writing data at a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to phase synchronize a second clock, having a clock frequency higher than a clock frequency of a first clock, with the first clock in response to the auto-sync signal.