公开(公告)号：US20230274139A1

公开(公告)日：2023-08-31

申请号：US18143448

申请日：2023-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Stylianos I. VENIERIS ,  Mario ALMEIDA ,  Royson LEE

IPC: G06N3/08

CPC classification number: G06N3/08

Abstract: Broadly speaking, the present techniques generally relate to a computer-implemented method for training a machine learning, ML, model to perform super-resolution on resource-constrained devices.

公开(公告)号：US20230359497A1

公开(公告)日：2023-11-09

申请号：US18221089

申请日：2023-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongxiang FAN ,  Chun Pong CHAU ,  Stylianos VENIERIS ,  Alexandros KOURIS ,  Royson LEE ,  Mohamed S. ABDELFATTAH

IPC: G06F9/50 ,  G06F17/16 ,  G06F17/14 ,  G06F7/523

CPC classification number: G06F9/5027 ,  G06F17/16 ,  G06F17/142 ,  G06F7/523

Abstract: Broadly speaking, the present disclosure generally relate to an electronic device for accelerating machine learning, ML, model computations is provided. The electronic device comprises: a first processor configured to: generate a query matrix, a key matrix, and a value matrix by performing Fast Fourier Transform (FFT) and butterfly linear transform on at least one input matrix, and a second processor configured to: perform a first matrix multiplication between the query matrix and the key matrix, perform a softmax operation on the result of the first matrix multiplication, and perform a second matrix multiplication between the result of the softmax operation and the value matrix.

公开(公告)号：US20220101063A1

公开(公告)日：2022-03-31

申请号：US17514840

申请日：2021-10-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chun Pong CHAU ,  Mohamed S. ABDELFATTAH ,  Lukasz DUDZIAK ,  Royson LEE ,  Hyeji KIM ,  Nicholas Donald Atkins LANE

IPC: G06K9/62 ,  G06N3/02

Abstract: A method of predicting performance of a hardware arrangement or a neural network model includes: obtaining one or more of a first hardware arrangement or a first neural network model, obtaining a first graphical model comprising a first plurality of nodes corresponding to the obtained first hardware arrangement or the obtained first neural network model, wherein each node of the first plurality of nodes corresponds to a respective component or device of the first plurality of interconnected components or devices or a respective operation of the first plurality of operations; extracting, based on the first graphical model, a first graphical representation of the obtained first hardware arrangement or the obtained first neural network model; predicting, based on the first graphical representation, performance of the obtained first hardware arrangement or the obtained first neural network model; and outputting the predicted performance.

公开(公告)号：US20210081763A1

公开(公告)日：2021-03-18

申请号：US17015724

申请日：2020-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mohamed S. ABDELFATTAH ,  Lukasz DUDZIAK ,  Chun Pong CHAU ,  Hyeji KIM ,  Royson LEE ,  Sourav BHATTACHARYA

IPC: G06N3/04 ,  G06N7/00 ,  G06N3/08

Abstract: Disclosed are an electronic device and a method for controlling thereof. The electronic device includes: a memory for storing a plurality of accelerators and a plurality of neural networks and a processor configured to: select a first neural network among the plurality of neural networks and select a first accelerator to implement the first neural network among the plurality of accelerators, implement the first neural network on the first accelerator to obtain information associated with the implementation, obtain a first reward value for the first accelerator and the first neural network based on the information associated with the implementation, select a second neural network to be implemented on the first accelerator among the plurality of neural networks, implement the second neural network on the first accelerator to obtain the information associated with the implementation, obtain a second reward value for the first accelerator and the second neural network based on the information associated with the implementation, and select a neural network and an accelerator having a largest reward value among the plurality of neural networks and the plurality of accelerators based on the first reward value and the second reward value.