公开(公告)号：US20230354594A1

公开(公告)日：2023-11-02

申请号：US18220073

申请日：2023-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGHWAN KIM ,  YOUNGHWAN SON ,  SHINHWAN KWAN ,  JEEHOON HAN

IPC: H10B41/27 ,  H01L23/538 ,  G11C5/02 ,  H10B43/27

CPC classification number: H10B41/27 ,  H01L23/5384 ,  G11C5/025 ,  H10B43/27

Abstract: A vertical memory device includes gate electrodes, a channel, a first conductive through via, and insulation structures. The gate electrodes are spaced apart from each other on a substrate in a first direction substantially perpendicular to an upper surface of the substrate, and may be stacked in a staircase shape. The channel extends through the gate electrodes in the first direction. The first conductive through via extends through a conductive pad of a first gate electrode among the gate electrodes and is electrically connected thereto. The first conductive through via extends through second gate electrodes from among the gate electrodes that are under the first gate electrode. The insulation structures are formed between the first conductive through via and sidewalls of each of the second gate electrodes, and electrically insulates the first conductive through via from each of the second gate electrodes.

公开(公告)号：US20210193672A1

公开(公告)日：2021-06-24

申请号：US17019693

申请日：2020-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGHWAN KIM ,  YOUNGHWAN SON ,  SHINHWAN KWAN ,  JEEHOON HAN

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/02 ,  H01L23/538

Abstract: A vertical memory device includes gate electrodes, a channel, a first conductive through via, and insulation structures. The gate electrodes are spaced apart from each other on a substrate in a first direction substantially perpendicular to an upper surface of the substrate, and may be stacked in a staircase shape. The channel extends through the gate electrodes in the first direction. The first conductive through via extends through a conductive pad of a first gate electrode among the gate electrodes and is electrically connected thereto. The first conductive through via extends through second gate electrodes from among the gate electrodes that are under the first gate electrode. The insulation structures are formed between the first conductive through via and sidewalls of each of the second gate electrodes, and electrically insulates the first conductive through via from each of the second gate electrodes.