公开(公告)号：US20230354594A1

公开(公告)日：2023-11-02

申请号：US18220073

申请日：2023-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGHWAN KIM ,  YOUNGHWAN SON ,  SHINHWAN KWAN ,  JEEHOON HAN

IPC: H10B41/27 ,  H01L23/538 ,  G11C5/02 ,  H10B43/27

CPC classification number: H10B41/27 ,  H01L23/5384 ,  G11C5/025 ,  H10B43/27

Abstract: A vertical memory device includes gate electrodes, a channel, a first conductive through via, and insulation structures. The gate electrodes are spaced apart from each other on a substrate in a first direction substantially perpendicular to an upper surface of the substrate, and may be stacked in a staircase shape. The channel extends through the gate electrodes in the first direction. The first conductive through via extends through a conductive pad of a first gate electrode among the gate electrodes and is electrically connected thereto. The first conductive through via extends through second gate electrodes from among the gate electrodes that are under the first gate electrode. The insulation structures are formed between the first conductive through via and sidewalls of each of the second gate electrodes, and electrically insulates the first conductive through via from each of the second gate electrodes.

公开(公告)号：US20230180478A1

公开(公告)日：2023-06-08

申请号：US18103070

申请日：2023-01-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYOJOON RYU ,  YOUNGHWAN SON ,  SEOGOO KANG ,  JESUK MOON ,  JUNGHOON JUN ,  KOHJI KANAMORI ,  JEEHOON HAN

IPC: H10B43/35 ,  H10B43/40 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes; gate layers stacked on a substrate, a channel layer extending through the gate layers, a string select gate layer disposed on the channel layer and a string select channel layer extending through the string select gate layer to contact the channel layer. The string select channel layer includes a first portion below the string select gate layer including a first protruding region, a second portion extending through the string select gate layer, and a third portion above the string select gate layer including a second protruding region.

公开(公告)号：US20210193672A1

公开(公告)日：2021-06-24

申请号：US17019693

申请日：2020-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGHWAN KIM ,  YOUNGHWAN SON ,  SHINHWAN KWAN ,  JEEHOON HAN

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/02 ,  H01L23/538

Abstract: A vertical memory device includes gate electrodes, a channel, a first conductive through via, and insulation structures. The gate electrodes are spaced apart from each other on a substrate in a first direction substantially perpendicular to an upper surface of the substrate, and may be stacked in a staircase shape. The channel extends through the gate electrodes in the first direction. The first conductive through via extends through a conductive pad of a first gate electrode among the gate electrodes and is electrically connected thereto. The first conductive through via extends through second gate electrodes from among the gate electrodes that are under the first gate electrode. The insulation structures are formed between the first conductive through via and sidewalls of each of the second gate electrodes, and electrically insulates the first conductive through via from each of the second gate electrodes.

公开(公告)号：US20220028731A1

公开(公告)日：2022-01-27

申请号：US17496902

申请日：2021-10-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUNIL SHIM ,  Shinhwan KANG ,  YOUNGHWAN SON

IPC: H01L21/762 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565 ,  H01L21/761 ,  H01L27/24 ,  H01L27/11573 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11529

Abstract: Disclosed is a three-dimensional semiconductor device including a horizontal semiconductor layer including a plurality of well regions having a first conductivity and a separation impurity region having a second conductivity, and a plurality of cell array structures provided on the well regions of the horizontal semiconductor layer, respectively. The separation impurity region is between and in contact with the well regions. Each of the cell array structures comprises a stack structure including a plurality of stacked electrodes in a vertical direction to a top surface of the horizontal semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to a corresponding well region.

公开(公告)号：US20190057898A1

公开(公告)日：2019-02-21

申请号：US15954912

申请日：2018-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUNIL SHIM ,  Shinhwan KANG ,  YOUNGHWAN SON

IPC: H01L21/762 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565 ,  H01L21/761 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/24

Abstract: Disclosed is a three-dimensional semiconductor device including a horizontal semiconductor layer including a plurality of well regions having a first conductivity and a separation impurity region having a second conductivity, and a plurality of cell array structures provided on the well regions of the horizontal semiconductor layer, respectively. The separation impurity region is between and in contact with the well regions. Each of the cell array structures comprises a stack structure including a plurality of stacked electrodes in a vertical direction to a top surface of the horizontal semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to a corresponding well region.

公开(公告)号：US20210143160A1

公开(公告)日：2021-05-13

申请号：US16942456

申请日：2020-07-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYOJOON RYU ,  YOUNGHWAN SON ,  SEOGOO KANG ,  JESUK MOON ,  JUNGHOON JUN ,  KOHJI KANAMORI ,  JEEHOON HAN

IPC: H01L27/1157 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor device includes; gate layers stacked on a substrate, a channel layer extending through the gate layers, a string select gate layer disposed on the channel layer and a string select channel layer extending through the string select gate layer to contact the channel layer. The string select channel layer includes a first portion below the string select gate layer including a first protruding region, a second portion extending through the string select gate layer, and a third portion above the string select gate layer including a second protruding region.

公开(公告)号：US20200161330A1

公开(公告)日：2020-05-21

申请号：US16750176

申请日：2020-01-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KOHJI KANAMORI ,  SEO-GOO KANG ,  YOUNGHWAN SON ,  KWONSOON JO

IPC: H01L27/11582 ,  G11C8/14 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/1157

Abstract: A three-dimensional semiconductor memory device includes a peripheral logic structure on a semiconductor substrate. A horizontal semiconductor layer is on the peripheral logic structure and includes a cell array region and a connection region. Electrode structures extend in a first direction on the horizontal semiconductor layer and are spaced apart in a second direction intersecting the first direction. A pair of the electrode structures adjacent to each other are symmetrically disposed to define a contact region partially exposing the horizontal semiconductor layer. A through via structure is on the contact region and connects the electrode structures to the peripheral logic structure. Each of the electrode structures includes a plurality of gate insulation regions extending along the first direction on the connection region. The gate insulation regions have different lengths from each other in the first direction.