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    VERTICAL MEMORY DEVICE INCLUDING SUBSTRATE CONTROL CIRCUIT AND MEMORY SYSTEM INCLUDING THE SAME
    1.
    发明申请
    VERTICAL MEMORY DEVICE INCLUDING SUBSTRATE CONTROL CIRCUIT AND MEMORY SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20190139968A1

    公开(公告)日：2019-05-09

    申请号：US16035995

    申请日：2018-07-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-won SHIM ,  Bong-soon LIM

    IPC: H01L27/115 ,  G11C16/08 ,  G11C16/24 ,  G11C7/10 ,  G11C7/18 ,  G11C8/14 ,  G11C16/04

    Abstract: A nonvolatile memory device comprises a first semiconductor layer including, an upper substrate, and a memory cell array in which a plurality of word lines on the upper substrate extend in a first direction and a plurality of bit lines extend in a second direction. The nonvolatile memory device comprises a second semiconductor layer under the first semiconductor layer in a third direction perpendicular to the first and second directions, the second semiconductor layer including, a lower substrate, and a substrate control circuit on the lower substrate and configured to output a bias voltage to the upper substrate. The second semiconductor layer is divided into first through fourth regions, each of the first through fourth regions having an identical area, and the substrate control circuit overlaps at least a portion of the first through fourth regions in the third direction.

    NONVOLATILE MEMORY DEVICE HAVING A VERTICAL STRUCTURE AND A MEMORY SYSTEM INCLUDING THE SAME
    4.
    发明申请
    NONVOLATILE MEMORY DEVICE HAVING A VERTICAL STRUCTURE AND A MEMORY SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20210036015A1

    公开(公告)日：2021-02-04

    申请号：US17073653

    申请日：2020-10-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Bong-soon LIM ,  Jin-young KIM ,  Sang-won SHIM ,  Il-han PARK

    IPC: H01L27/11582 ,  H01L27/11573 ,  H01L25/18 ,  H01L23/535 ,  G11C16/04 ,  H01L23/522 ,  H01L27/11565 ,  G11C16/08 ,  H01L27/11575 ,  H01L27/1157

    Abstract: A nonvolatile memory device including: a first semiconductor layer comprising a plurality of first word lines extending in a first direction, a first upper substrate and a first memory cell array, a second semiconductor layer including a plurality of second word lines extending in the first direction, second and third upper substrates adjacent to each other in the first direction and a second memory cell army, wherein the second memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, wherein the first semiconductor layer and the second semiconductor layer share a plurality of bit lines extending in a second direction, and a third semiconductor layer under the second semiconductor layer in a third direction perpendicular to the first and second directions, wherein the third semiconductor layer includes a lower substrate that includes a plurality of row decoder circuits and a plurality of page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area in the first direction.

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