公开(公告)号：US20240196599A1

公开(公告)日：2024-06-13

申请号：US18512135

申请日：2023-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaekang KOH ,  Byeongguk KO ,  Chanyoung KIM ,  Sangkoo NAM ,  Yongsoon CHOI

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315

Abstract: A semiconductor device includes: an active pattern disposed on a substrate; a gate structure disposed on the active pattern; a bit line structure disposed on the active pattern, and including a first conductive pattern, a second conductive pattern and an insulation structure stacked on each other, a lower spacer structure disposed on a sidewall of the bit line structure; an upper spacer structure disposed on the lower spacer structure, wherein the upper spacer structure is disposed on an upper portion of the sidewall of the bit line structure; a contact plug structure disposed on the active pattern, wherein the contact plug structure is spaced apart from the bit line structure; and a capacitor disposed on the contact plug structure, wherein the lower spacer structure includes: a first spacer partially covering a sidewall of the first conductive pattern, and including air; and a second spacer disposed on the first spacer.