公开(公告)号：US20210050049A1

公开(公告)日：2021-02-18

申请号：US16809016

申请日：2020-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seheon BAEK ,  Youngsun MIN

IPC: G11C11/4091 ,  G11C11/4094 ,  G11C11/4093 ,  G11C11/4074 ,  G11C7/22 ,  G11C7/10 ,  G11C5/02

Abstract: A memory device includes a first page buffer supplying a first bias voltage to a selected bitline in a bitline precharge phase; and a second page buffer supplying a second bias voltage to an unselected bitline, adjacent to the selected bitline, in the bitline precharge phase, wherein the first page buffer includes a first bitline precharge circuit supplying the first bias voltage to the selected bitline, the second page buffer includes a second bitline precharge circuit supplying the second bias voltage to the unselected bitline, wherein the second page buffer floats the unselected bitline in a sensing phase for detecting data of a selected memory cell connected to the selected to bitline.