公开(公告)号：US10332231B2

公开(公告)日：2019-06-25

申请号：US15407980

申请日：2017-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangoak Woo ,  Jongpil Son ,  Seungcheol Baek ,  Soojung Ryu

IPC: G06T1/20 ,  G06T1/60

Abstract: A computing system includes a memory device comprising a memory array and an internal processor configured to perform a first sub pipeline of a graphics pipeline for tile-based rendering by using graphics data stored in the memory array, for offload processing of the first sub pipeline from a host processor; and the host processor configured to perform a second sub pipeline of the graphics pipeline by using a result of the first sub pipeline stored in the memory array.

公开(公告)号：US10417736B2

公开(公告)日：2019-09-17

申请号：US15591571

申请日：2017-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungcheol Baek ,  Kwontaek Kwon

IPC: G06T1/60 ,  G06T15/04 ,  G06T1/20 ,  G06F12/0888 ,  G06F9/38

Abstract: A control device for cache bypass includes: an information acquirer configured to acquire information about pixels on a screen space and a texture to be mapped to the pixels; and a controller configured to determine a scale factor, by using the acquired information, and to control texture data corresponding to the texture to bypass a cache based on the scale factor, wherein the scale factor is a ratio of a size of the texture to a size of the pixels.