公开(公告)号：US12191390B2

公开(公告)日：2025-01-07

申请号：US18518004

申请日：2023-11-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggun You ,  Yoonjoong Kim ,  Seungwoo Do ,  Sungil Park

IPC: H01L29/78 ,  H01L29/10

Abstract: A semiconductor device including a substrate that includes first to third regions; a first channel structure on the first region and including first channel patterns that are vertically stacked on the substrate; a second channel structure on the second region and including a second channel pattern on the substrate; a third channel structure on the third region and including third channel patterns and fourth channel patterns that are vertically and alternately stacked on the substrate; first to third gate electrodes on the first to third channel structures; and first to third source/drain patterns on opposite sides of the first to third channel structures, wherein the first, second, and fourth channel patterns include a first semiconductor material, and the third channel patterns include a second semiconductor material different from the first semiconductor material.

公开(公告)号：US11855209B2

公开(公告)日：2023-12-26

申请号：US17380256

申请日：2021-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggun You ,  Yoonjoong Kim ,  Seungwoo Do ,  Sungil Park

IPC: H01L29/78 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L29/1033

Abstract: A semiconductor device including a substrate that includes first to third regions; a first channel structure on the first region and including first channel patterns that are vertically stacked on the substrate; a second channel structure on the second region and including a second channel pattern on the substrate; a third channel structure on the third region and including third channel patterns and fourth channel patterns that are vertically and alternately stacked on the substrate; first to third gate electrodes on the first to third channel structures; and first to third source/drain patterns on opposite sides of the first to third channel structures, wherein the first, second, and fourth channel patterns include a first semiconductor material, and the third channel patterns include a second semiconductor material different from the first semiconductor material.