公开(公告)号：US20190385653A1

公开(公告)日：2019-12-19

申请号：US16555455

申请日：2019-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yeop BAECK ,  Siddharth Gupta ,  ln-hak Lee ,  Jae-seung Choi ,  Tae-hyung Kim ,  Dae-young Moon ,  Dong-wook Seo

IPC: G11C8/08 ,  G11C11/419 ,  G11C5/14

Abstract: Provided are a voltage control circuit including an assist circuit and a memory device including the voltage control circuit. The memory device includes: a volatile memory cell array, which is connected to a plurality of word lines and includes a memory cell including at least one transistor; and an assist circuit, which is connected to at least one of the plurality of word lines and adjusts a driving voltage level of each of the plurality of word lines, wherein the assist circuit includes a diode N-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain connected to each other.

公开(公告)号：US10672442B2

公开(公告)日：2020-06-02

申请号：US16555455

申请日：2019-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-yeop Baeck ,  Siddharth Gupta ,  In-hak Lee ,  Jae-seung Choi ,  Tae-hyung Kim ,  Dae-young Moon ,  Dong-wook Seo

IPC: G11C8/08 ,  G11C5/14 ,  G11C11/419 ,  G11C11/418

Abstract: Provided are a voltage control circuit including an assist circuit and a memory device including the voltage control circuit. The memory device includes: a volatile memory cell array, which is connected to a plurality of word lines and includes a memory cell including at least one transistor; and an assist circuit, which is connected to at least one of the plurality of word lines and adjusts a driving voltage level of each of the plurality of word lines, wherein the assist circuit includes a diode N-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain connected to each other.

公开(公告)号：US20190080736A1

公开(公告)日：2019-03-14

申请号：US15921771

申请日：2018-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-yeop Baeck ,  Siddharth Gupta ,  In-hak Lee ,  Jae-seung Choi ,  Tae-hyung Kim ,  Dae-young Moon ,  Dong-wook Seo

IPC: G11C8/08 ,  G11C11/419 ,  G11C5/14

CPC classification number: G11C8/08 ,  G11C5/14 ,  G11C11/418 ,  G11C11/419

Abstract: Provided are a voltage control circuit including an assist circuit and a memory device including the voltage control circuit. The memory device includes: a volatile memory cell array, which is connected to a plurality of word lines and includes a memory cell including at least one transistor; and an assist circuit, which is connected to at least one of the plurality of word lines and adjusts a driving voltage level of each of the plurality of word lines, wherein the assist circuit includes a diode N-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain connected to each other.

公开(公告)号：US10431272B2

公开(公告)日：2019-10-01

申请号：US15921771

申请日：2018-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-yeop Baeck ,  Siddharth Gupta ,  In-hak Lee ,  Jae-seung Choi ,  Tae-hyung Kim ,  Dae-young Moon ,  Dong-wook Seo

IPC: G11C8/08 ,  G11C5/14 ,  G11C11/419

Abstract: Provided are a voltage control circuit including an assist circuit and a memory device including the voltage control circuit. The memory device includes: a volatile memory cell array, which is connected to a plurality of word lines and includes a memory cell including at least one transistor; and an assist circuit, which is connected to at least one of the plurality of word lines and adjusts a driving voltage level of each of the plurality of word lines, wherein the assist circuit includes a diode N-channel metal oxide semiconductor (NMOS) transistor having a gate and a drain connected to each other.