公开(公告)号：US20240175912A1

公开(公告)日：2024-05-30

申请号：US18384910

申请日：2023-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seong Seob SHIN ,  Soon lL Kwon ,  Soo Yong Park ,  Tae-Hwan Kim

IPC: G01R31/28

CPC classification number: G01R31/2806

Abstract: A test device includes a main board. First and second device under test (DUT) boards are disposed on the main board. First and second semiconductor devices are mounted on the first and second DUT boards, respectively. The first and second semiconductor devices are DUTs. First and second connectors are respectively disposed at a first end and a second end of the first DUT board. The first and second connectors are spaced apart from each other and respectively transmit first and second signals. The first signal forms a first electrical path along which the first signal is input to the first DUT board via the first connector. The second signal forms a second electrical path along which the second signal is output from the first DUT board and input to the second DUT board via the second connector.