公开(公告)号：US20220101893A1

公开(公告)日：2022-03-31

申请号：US17470579

申请日：2021-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyeon PARK ,  Byunghoon Jeong ,  Chiweon Yoon

IPC: G11C7/10 ,  G11C7/20 ,  G11C8/06

Abstract: A memory chip, a memory controller, and an operating method of the memory chip are provided. The memory chip includes a plurality of pins; and an interface circuit configured to receive a swap command set from a memory controller through the plurality of pins, obtain a swap command and a swap address from the swap command set, generate a swap enable signal based on the swap command and the swap address, and swap and output a data signal according to the swap enable signal.

公开(公告)号：US20230410855A1

公开(公告)日：2023-12-21

申请号：US18457742

申请日：2023-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyeon PARK ,  Byunghoon JEONG ,  Chiweon YOON

IPC: G11C7/10 ,  G11C8/06 ,  G11C7/20

CPC classification number: G11C7/1012 ,  G11C7/109 ,  G11C7/1063 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/20 ,  G11C8/06

Abstract: A memory chip, a memory controller, and an operating method of the memory chip are provided. The memory chip includes a plurality of pins; and an interface circuit configured to receive a swap command set from a memory controller through the plurality of pins, obtain a swap command and a swap address from the swap command set, generate a swap enable signal based on the swap command and the swap address, and swap and output a data signal according to the swap enable signal.