公开(公告)号：US20230061418A1

公开(公告)日：2023-03-02

申请号：US17716054

申请日：2022-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YONGBUM KWON ,  UNBYOUNG KANG

IPC: H01L23/00 ,  H01L21/768

Abstract: A method of manufacturing a semiconductor package includes bonding first the and second structures, such that a first bonding structure is directly bonded to a second bonding structure. The forming of the first structure includes; forming a blocking layer on a metallic material layer including a first portion covering a concaved portion of the metallic material layer and a second portion covering a non-concaved portion of the metallic material layer, performing a first planarization process to remove the second portion of the blocking layer while the first portion of the blocking layer remains, performing a second planarization process to remove the non-concaved portion of the metallic material layer and expose the barrier layer on the insulating layer, performing a wet etching process to remove the barrier layer on the insulating layer and the blocking layer to form the first bonding pad including the barrier layer in the opening and the metallic material layer and forming a recessed portion below an upper surface of the metallic material layer on the barrier layer while removing the barrier layer on the insulating layer.

公开(公告)号：US20230048729A1

公开(公告)日：2023-02-16

申请号：US17707007

申请日：2022-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YEONGKWON KO ,  UNBYOUNG KANG ,  SOYEON KWON ,  YOONSUNG KIM ,  TEAKHOON LEE

IPC: H01L23/00 ,  H01L23/544

Abstract: A semiconductor package and a method of forming the same are provided. The semiconductor package includes: a semiconductor substrate having a front side and a back side, the semiconductor substrate having a chip area and a dummy area; a front structure below the front side, and including an internal circuit, an internal connection pattern, a guard pattern, and a front insulating structure; a rear protective layer overlapping the chip area and the dummy area, and a rear protrusion pattern on the rear protective layer and overlapping the dummy area, the rear protective layer and the rear protrusion pattern being on the back side; a through-electrode structure penetrating through the chip area and the rear protective layer, and electrically connected to the internal connection pattern; and a rear pad electrically connected to the through-electrode structure. The internal circuit and the internal connection pattern are below the chip area, and the guard pattern is below the chip area adjacent to the dummy area.

公开(公告)号：US20230010936A1

公开(公告)日：2023-01-12

申请号：US17568355

申请日：2022-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGGI JIN ,  GYUHO KANG ,  UNBYOUNG KANG ,  HEEWON KIM ,  JUMYONG PARK ,  HYUNSU HWANG

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/532 ,  H01L23/522

Abstract: A semiconductor chip includes: a semiconductor substrate; a pad insulating layer on the semiconductor substrate; a through electrode which penetrates the semiconductor substrate and the pad insulating layer and includes a conductive plug and a conductive barrier layer surrounding a sidewall of the conductive plug; and a bonding pad which surrounds a sidewall of the through electrode and is spaced apart from the conductive plug with the conductive barrier layer disposed therebetween.