公开(公告)号：US09331015B2

公开(公告)日：2016-05-03

申请号：US14103014

申请日：2013-12-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-hoon Han ,  Sung-jin Kim ,  Cheon-bae Kim ,  Won-chul Lee ,  Byung-hoon Cho

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor structure having a first wire extending in a first direction, an intermetallic insulating layer covering the semiconductor structure, a via structure penetrating the intermetallic insulating layer, and a second wire extending on the intermetallic insulating layer in a second direction at a predetermined angle with respect to the first direction, the second wire being connected to the first wire through the via structure and including first and second portions on each other, and a protruding portion protruding from at least one of the first and second portions, the protruding portion being at a boundary of the first and second portions.

Abstract translation: 半导体器件包括具有沿第一方向延伸的第一线的半导体结构，覆盖半导体结构的金属间绝缘层，穿过金属间绝缘层的通孔结构以及在第二方向上在金属间绝缘层上延伸的第二电极 相对于第一方向的预定角度，第二线通过通孔结构连接到第一线，并且包括第一和第二部分，以及从第一和第二部分中的至少一个突出的突出部分， 突出部分位于第一和第二部分的边界处。

公开(公告)号：US10079237B2

公开(公告)日：2018-09-18

申请号：US15645261

申请日：2017-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-hoon Kim ,  Won-chul Lee

IPC: H01L49/02 ,  H01L27/108 ,  H01L23/00

CPC classification number: H01L27/10808 ,  H01L23/562 ,  H01L27/10852 ,  H01L28/86 ,  H01L28/90

Abstract: A semiconductor memory device may include: a substrate having a cell area defined thereon, the cell area including a cell block area and an edge area; a plurality of bottom electrodes, on the substrate, which are in parallel with a top surface of the substrate and a first direction in parallel with a top surface of the substrate, and are arranged along a second direction intersecting the first direction; and a support structure pattern, in a flat plate shape, which connects the bottom electrodes to each other, supports the bottom electrodes onto the substrate, and includes a plurality of open areas, wherein a first profile, which is a horizontal cross-sectional profile in the edge area of the support structure pattern, has a wave shape.

公开(公告)号：US10468415B2

公开(公告)日：2019-11-05

申请号：US15834203

申请日：2017-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee-wook You ,  Won-chul Lee

IPC: H01L27/108 ,  H01L27/02 ,  H01L49/02

Abstract: The invention provides a semiconductor device including a capacitor capable of securing capacity and exhibiting improved reliability and a semiconductor package comprising the same. The semiconductor device includes: a substrate having a cell block; a plurality of capacitors, which are in the cell block of the substrate and have first electrodes; and a support pattern, which contacts sidewalls of the first electrodes of the plurality of capacitors and supports the plurality of capacitors, wherein the support pattern includes an upper support pattern including: a first upper pattern having a plate-like structure connected as a whole in the cell block; and a second upper pattern, which contacts a bottom surface of the first upper pattern and has a top surface having a smaller area than the bottom surface of the first upper pattern, the upper support pattern contacting sidewalls of upper ends of the first electrodes.

公开(公告)号：US20180158827A1

公开(公告)日：2018-06-07

申请号：US15834203

申请日：2017-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee-wook YOU ,  Won-chul Lee

IPC: H01L27/108 ,  H01L49/02 ,  H01L27/02

CPC classification number: H01L27/10814 ,  H01L27/0207 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10876 ,  H01L28/90 ,  H01L28/91

Abstract: The invention provides a semiconductor device including a capacitor capable of securing capacity and exhibiting improved reliability and a semiconductor package comprising the same. The semiconductor device includes: a substrate having a cell block; a plurality of capacitors, which are in the cell block of the substrate and have first electrodes; and a support pattern, which contacts sidewalls of the first electrodes of the plurality of capacitors and supports the plurality of capacitors, wherein the support pattern includes an upper support pattern including: a first upper pattern having a plate-like structure connected as a whole in the cell block; and a second upper pattern, which contacts a bottom surface of the first upper pattern and has a top surface having a smaller area than the bottom surface of the first upper pattern, the upper support pattern contacting sidewalls of upper ends of the first electrodes.