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1252 条记录 (耗时 0.026 秒)

    MEMORY DEVICE INCLUDING STRUCTURES IN MEMORY ARRAY REGION AND PERIPERAL CIRCUITRY REGION
    1.
    发明公开
    MEMORY DEVICE INCLUDING STRUCTURES IN MEMORY ARRAY REGION AND PERIPERAL CIRCUITRY REGION 审中-公开

    公开(公告)号：US20240064972A1

    公开(公告)日：2024-02-22

    申请号：US17892603

    申请日：2022-08-22

    申请人： Micron Technology, Inc.

    发明人： Si-Woo Lee ,  Terrence B. Mcdaniel ,  Guangjun Yang ,  Vinay Nair

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10897 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10894

    摘要： Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes data lines; first structures located in a first region, electrically separated from each other, and including first conductive contacts coupled to the data lines; second conductive contacts located in the first region and coupled to memory elements of the apparatus; second structures located in a second region, electrically separated from each other, and including respective gates of transistors in the second region; a first dielectric material formed in the second region and including a first portion and a second portion, the first portion formed at a first side of a structure among the second structures, the second portion formed at a second side first of the structure; and a second dielectric material formed over the first structures and the second structure. A portion of the second dielectric material contacts the first portion of the first dielectric material.

    METHOD OF PREPARING SEMICONDUCTOR STRUCTURE HAVING LOW DIELECTRIC CONSTANT LAYER
    2.
    发明公开
    METHOD OF PREPARING SEMICONDUCTOR STRUCTURE HAVING LOW DIELECTRIC CONSTANT LAYER 审中-公开

    公开(公告)号：US20230320059A1

    公开(公告)日：2023-10-05

    申请号：US17707146

    申请日：2022-03-29

    申请人： NANYA TECHNOLOGY CORPORATION

    发明人： Yu-Kai LU

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10844 ,  H01L27/10808

    摘要： The present application provides a method of preparing a semiconductor structure. The method includes providing a conductive film; disposing a barrier layer over the conductive film; disposing a first dielectric layer over the barrier layer; disposing a patterned hard mask over the first dielectric layer; and removing a portion of the first dielectric layer exposed through the patterned hard mask, wherein the removal of the portion of the first dielectric layer includes providing a nitrogen plasma to collide with the portion of the first dielectric layer.

    CONTACT STRUCTURE, METHOD OF MANUFACTURING CONTACT STRUCTURE, AND SEMICONDUCTOR STRUCTURE
    3.
    发明公开
    CONTACT STRUCTURE, METHOD OF MANUFACTURING CONTACT STRUCTURE, AND SEMICONDUCTOR STRUCTURE 审中-公开

    公开(公告)号：US20230262963A1

    公开(公告)日：2023-08-17

    申请号：US17662473

    申请日：2022-05-09

    申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

    发明人： Haiyan Wang

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10888 ,  H01L27/10855 ,  H01L27/10808

    摘要： The present disclosure relates to a contact structure, a method of manufacturing a contact structure, and a semiconductor structure. The method of manufacturing a contact structure includes: providing a substrate, where the substrate is provided with a shallow trench isolation structure; forming a medium layer covering the substrate and the shallow trench isolation structure; forming a contact hole in an active region of the substrate and in the medium layer, where the contact hole includes a first contact hole penetrating through the medium layer, and a second contact hole located at the bottom of the first contact hole and formed in the substrate; and forming a contact structure extending along a first direction in the contact hole and on the medium layer.

    3D STACKED DRAM WITH 3D VERTICAL CIRCUIT DESIGN
    4.
    发明公开
    3D STACKED DRAM WITH 3D VERTICAL CIRCUIT DESIGN 审中-公开

    公开(公告)号：US20230225109A1

    公开(公告)日：2023-07-13

    申请号：US17574525

    申请日：2022-01-12

    申请人： Tokyo Electron Limited

    发明人： H. Jim Fulford ,  Mark I. Gardner ,  Partha Mukhopadhyay

    IPC分类号： H01L27/108 ,  H01L29/78 ,  H01L29/66

    CPC分类号： H01L27/10808 ,  H01L29/7827 ,  H01L27/10852 ,  H01L27/10873 ,  H01L29/66666

    摘要： Apparatuses, devices and methods for fabricating one or more vertically integrated single bit capacitor-based memory cells is disclosed. A single bit capacitor-based memory cell can include a vertically oriented transistor and a vertically oriented capacitor that is vertically integrated with the transistor, so as to form a memory cell. Aspects of the disclosure include process steps for forming the transistor and the capacitor, including a first metal part of a capacitor, a second metal part of a capacitor and an electrically insulating layer disposed between the two. The transistor and the capacitor also include an electrical contact between them and a layer that insulates the transistor from the base layer or the underlying substrate.

    Dynamic random access memory
    8.
    发明授权
    Dynamic random access memory 有权

    公开(公告)号：US10074654B1

    公开(公告)日：2018-09-11

    申请号：US15942439

    申请日：2018-03-31

    申请人： Winbond Electronics Corp.

    发明人： Kazuaki Takesako ,  Kazutaka Manabe ,  Noriaki Ikeda ,  Wei-Che Chang

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10808 ,  H01L27/10823 ,  H01L27/1085 ,  H01L27/10852 ,  H01L27/10873 ,  H01L27/10876

    摘要： Provided is a dynamic random access memory. A plurality of isolation structures is disposed in a substrate to define a plurality of active regions arranged along a first direction. The substrate has a trench extended along the first direction and passing through the plurality of isolation structures and the plurality of active regions. A buried word line is disposed in the trench. A plurality of gate dielectric layers is disposed in the trench of the plurality of active regions to surround and cover the buried word line. A cap layer covers the buried word line. The height of the top surface of the second side of the buried word line is lower than the height of the top surface of the first side of the buried word line passing through the plurality of active regions and the plurality of isolation structures.