公开(公告)号：US20230099844A1

公开(公告)日：2023-03-30

申请号：US17830488

申请日：2022-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Ho KIM ,  Woo Jin JANG ,  Jeong Hoon AHN ,  Yun Ki CHOI

IPC: H01L23/00 ,  H01L25/065

Abstract: Provided is a semiconductor package including a first chip substrate including a first surface and a second surface, a through via passing through the first chip substrate, an upper passivation layer including a trench on the second surface of the first chip substrate, the trench exposing at least a portion of the second surface of the first chip substrate, an upper pad electrically connected with the through via on the trench, a second chip substrate including a third surface and a fourth surface, a lower pad electrically connected to the second chip substrate on the third surface of the second chip substrate, and a connection bump electrically connecting the upper pad with the lower pad and contacting the lower pad, wherein a width of the connection bump increases as the connection bump becomes farther away from the first surface of the first chip substrate.

公开(公告)号：US20190079553A1

公开(公告)日：2019-03-14

申请号：US15914095

申请日：2018-03-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Jin JANG ,  Seung Hyun OH ,  Jong Woo LEE

IPC: G05F3/16 ,  H03K17/567

CPC classification number: G05F3/16 ,  H03K17/567

Abstract: A bandgap reference voltage generation system includes a common mode voltage generator, a bandgap reference voltage generation circuit, and a switch controller. The bandgap reference voltage generation circuit includes a plurality of transistors having source terminals respectively connected to drain terminals of a plurality of PMOS transistors. The switch controller provides a ground voltage to the bandgap reference voltage generation circuit in a first mode and a common mode voltage to the bandgap reference voltage generation circuit in a second mode. The bandgap reference voltage generation circuit causes the plurality of the transistors to operate in a linear region by providing the common mode voltage to gate electrodes of the plurality of the transistors in the first mode and a saturation region by providing the ground voltage to the gate electrodes of the plurality of the transistors in the second mode.