Abstract:
A display device includes a display panel having pixels arranged at intersections of source lines and gate lines, a plurality of source drivers configured to dispersedly output image data signals to the source lines in response to source control signals and a data packet, a plurality of gate drivers configured to drive gate lines in response to gate control signals so as to be connected with pixels corresponding to the source lines, and a timing controller configured to output the data packet, the source control signals, and the gate control signals. At least one of the plurality of source drivers is configured to output carry information associated with an output of the image data signals, and at least another of the plurality of source drivers is configured to output the image data signals in response to the carry information.
Abstract:
An electronic device includes a first source group and a second source group, each of which includes a plurality of source channels, and a gamma block that receives first to 2i-th initial voltages (i being an integer of 1 or more), outputs first to 2i-th intermediate voltages by amplifying the first to i-th initial voltages, and outputs first to i-th gamma voltages to the first source group by buffering the first to 2i-th intermediate voltages, and a first buffer block that receives the first to 2i-th intermediate voltages from the gamma block and buffers the first to 2i-th intermediate voltages so as to be output to the second source group, and the gamma block may include a first resistor string including a plurality of resistors connected between nodes from which the first to i-th gamma voltages are output.
Abstract:
An electronic device includes a first source group and a second source group, each of which includes a plurality of source channels, and a gamma block that receives first to 2i-th initial voltages (i being an integer of 1 or more), outputs first to 2i-th intermediate voltages by amplifying the first to i-th initial voltages, and outputs first to i-th gamma voltages to the first source group by buffering the first to 2i-th intermediate voltages, and a first buffer block that receives the first to 2i-th intermediate voltages from the gamma block and buffers the first to 2i-th intermediate voltages so as to be output to the second source group, and the gamma block may include a first resistor string including a plurality of resistors connected between nodes from which the first to i-th gamma voltages are output.