公开(公告)号：US20220199534A1

公开(公告)日：2022-06-23

申请号：US17654486

申请日：2022-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YONG KONG SIEW ,  WEI HSIUNG TSENG ,  CHANGHWA KIM

IPC: H01L23/535 ,  H01L23/485 ,  H01L21/768 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a substrate having an active region, a gate structure disposed on the active region, a source/drain region disposed in the active region at a side of the gate structure, a first interlayer insulating layer and a second interlayer insulating layer sequentially disposed on the gate structure and the source/drain region, a first contact plug connected to the source/drain region through the first interlayer insulating layer, a second contact plug connected to the gate structure through the first interlayer insulating layer and the second interlayer insulating layer, a first metal line disposed on the second interlayer insulating layer, and having a metal via disposed in the second interlayer insulating layer and connected to the first contact plug, and a second metal line disposed on the second interlayer insulating layer, and directly connected to the second contact plug.

公开(公告)号：US20190333856A1

公开(公告)日：2019-10-31

申请号：US16508555

申请日：2019-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YONG KONG SIEW ,  WEI HSIUNG TSENG ,  CHANGHWA KIM

IPC: H01L23/535 ,  H01L21/768 ,  H01L29/06 ,  H01L29/66 ,  H01L29/417 ,  H01L23/485 ,  H01L29/78

Abstract: A semiconductor device includes a substrate having an active region, a gate structure disposed on the active region, a source/drain region disposed in the active region at a side of the gate structure, a first interlayer insulating layer, and a second interlayer insulating layer sequentially disposed on the gate structure and the source/drain region, a first contact plug connected to the source/drain region through the first inter layer insulating layer, a second contact plug connected to the gate structure through the first interlayer insulating layer and the second interlayer insulating layer, a first metal line disposed on the second interlayer insulating layer, and having a metal via disposed in the second inter layer insulating layer and connected to the first contact plug, and a second metal line disposed on the second interlayer insulating layer, and directly connected to the second contact plug. An interval between the first contact plug and the second contact plug may be about 10 nm or less.

公开(公告)号：US20240030140A1

公开(公告)日：2024-01-25

申请号：US18476571

申请日：2023-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YONG KONG SIEW ,  WEI HSIUNG TSENG ,  CHANGHWA KIM

IPC: H01L23/535 ,  H01L23/485 ,  H01L21/768 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/535 ,  H01L23/485 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/76895 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/165

Abstract: A semiconductor device includes a substrate having an active region, a gate structure disposed on the active region, a source/drain region disposed in the active region at a side of the gate structure, a first interlayer insulating layer and a second interlayer insulating layer sequentially disposed on the gate structure and the source/drain region, a first contact plug connected to the source/drain region through the first interlayer insulating layer, a second contact plug connected to the gate structure through the first interlayer insulating layer and the second interlayer insulating layer, a first metal line disposed on the second interlayer insulating layer, and having a metal via disposed in the second interlayer insulating layer and connected to the first contact plug, and a second metal line disposed on the second interlayer insulating layer, and directly connected to the second contact plug.

公开(公告)号：US20180096934A1

公开(公告)日：2018-04-05

申请号：US15493965

申请日：2017-04-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YONG KONG SIEW ,  WEI HSIUNG TSENG ,  CHANGHWA KIM

IPC: H01L23/535 ,  H01L29/06 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L23/535 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76895 ,  H01L23/485 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a substrate having an active region, a gate structure disposed on the active region, a source/drain region disposed in the active region at a side of the gate structure, a first interlayer insulating layer and a second interlayer insulating layer sequentially disposed on the gate structure and the source/drain region, a first contact plug connected to the source/drain region through the first interlayer insulating layer, a second contact plug connected to the gate structure through the first interlayer insulating layer and the second interlayer insulating layer, a first metal line disposed on the second interlayer insulating layer, and having a metal via disposed in the second interlayer insulating layer and connected to the first contact plug, and a second metal line disposed on the second interlayer insulating layer, and directly connected to the second contact plug. An interval between the first contact plug and the second contact plug may be about 10 nm or less.