公开(公告)号：US11996065B2

公开(公告)日：2024-05-28

申请号：US17985599

申请日：2022-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungho Ryu ,  Kyongho Kim ,  Yongyun Park ,  Kilhoon Lee ,  Yeongcheol Rhee ,  Taeho Lee ,  Hyunwook Lim

IPC: G09G5/00

CPC classification number: G09G5/008 ,  G09G2370/04

Abstract: Provided is a display driving circuit. The display driving circuit includes a clock data recovery circuit configured to receive a data signal and generate a clock signal and a first output data signal, an eye margin test circuit configured to sample the data signal by using the clock signal, based on a vertical measurement voltage and generate a second output data signal, and a bit error check circuit configured to measure a bit error rate of the data signal, based on the first output data signal and the second output data signal, wherein the clock data recovery circuit includes a jitter generator configured to generate jitter of the clock signal such that a jitter amplitude varies according to a horizontal control signal.