公开(公告)号：US20140138759A1

公开(公告)日：2014-05-22

申请号：US14149884

申请日：2014-01-08

Applicant: SAMSUNG Electronics Co., Ltd.

Inventor： Young-Ho LEE ,  Keon-Soo KIM ,  Seong-Soon CHO ,  Jin- Hyun SHIN

IPC: H01L27/06

CPC classification number: H01L27/0629 ,  H01L27/11531 ,  H01L28/20

Abstract: In an integrated circuit device and method of manufacturing the same, a resistor pattern is positioned on a device isolation layer of a substrate. The resistor pattern includes a resistor body positioned in a recess portion of the device isolation layer and a connector making contact with the resistor body and positioned on the device isolation layer around the recess portion. The connector has a metal silicide pattern having electric resistance lower than that of the resistor body at an upper portion. A gate pattern is positioned on the active region of the substrate and includes the metal silicide pattern at an upper portion. A resistor interconnection is provided to make contact with the connector of the resistor pattern. A contact resistance between the connector and the resistor interconnection is reduced.

Abstract translation: 在集成电路器件及其制造方法中，电阻器图案位于衬底的器件隔离层上。 电阻器图案包括位于器件隔离层的凹部中的电阻体，以及与电阻体接触并连接在凹部的周围的器件隔离层上的连接器。 连接器具有在上部具有低于电阻体的电阻的金属硅化物图案。 栅极图案位于衬底的有源区上，并且在上部包括金属硅化物图案。 提供电阻器互连以与电阻器图案的连接器接触。 连接器和电阻器互连之间的接触电阻降低。