公开(公告)号：US20230016518A1

公开(公告)日：2023-01-19

申请号：US17375476

申请日：2021-07-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yu-Chung LIEN ,  Abhijith PRAKASH ,  Keyur PAYAK ,  Jiahui YUAN ,  Huai-Yuan TSENG ,  Shinsuke YADA ,  Kazuki ISOZUMI

IPC: H01L27/11556 ,  G11C5/02 ,  H01L27/11582 ,  H01L29/78

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, first memory opening fill structures extending through the alternating stack and including a respective first vertical semiconductor channel having a tubular section and a semi-tubular section, second memory opening fill structures, first bit lines electrically connected to a respective subset of the first drain regions, second bit lines electrically connected to a respective subset of the second drain regions, and an erase voltage application circuit configured to electrically bias the first bit lines at a first bit line erase voltage and the second bit lines at a second bit line erase voltage during an erase operation. The first bit line erase voltage is greater than the second bit line erase voltage.