公开(公告)号：US20230016518A1

公开(公告)日：2023-01-19

申请号：US17375476

申请日：2021-07-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yu-Chung LIEN ,  Abhijith PRAKASH ,  Keyur PAYAK ,  Jiahui YUAN ,  Huai-Yuan TSENG ,  Shinsuke YADA ,  Kazuki ISOZUMI

IPC: H01L27/11556 ,  G11C5/02 ,  H01L27/11582 ,  H01L29/78

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, first memory opening fill structures extending through the alternating stack and including a respective first vertical semiconductor channel having a tubular section and a semi-tubular section, second memory opening fill structures, first bit lines electrically connected to a respective subset of the first drain regions, second bit lines electrically connected to a respective subset of the second drain regions, and an erase voltage application circuit configured to electrically bias the first bit lines at a first bit line erase voltage and the second bit lines at a second bit line erase voltage during an erase operation. The first bit line erase voltage is greater than the second bit line erase voltage.

公开(公告)号：US20220254797A1

公开(公告)日：2022-08-11

申请号：US17169987

申请日：2021-02-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely SAID ,  Jiahui YUAN ,  Senaka KANAKAMEDALA ,  Raghuveer S. MAKALA ,  Dana LEE

IPC: H01L27/11556 ,  H01L29/66 ,  H01L29/423 ,  H01L29/788

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric layer, and a vertical stack of memory elements located at levels of the electrically conductive layers between a respective vertically neighboring pair of the insulating layers. Each of the memory elements includes a first memory material portion, and a second memory material portion that is vertically spaced from and is electrically isolated from the first memory material portion by at least one blocking dielectric material portion.

公开(公告)号：US20240105623A1

公开(公告)日：2024-03-28

申请号：US17934685

申请日：2022-09-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely SAID ,  Jiahui YUAN ,  Lito De La RAMA

IPC: H01L23/535 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582

CPC classification number: H01L23/535 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device includes a horizontal source layer which is laterally separated into laterally isolated portions located in adjacent memory blocks by a dielectric backside trench fill structure or a source isolation dielectric structure.

公开(公告)号：US20200321444A1

公开(公告)日：2020-10-08

申请号：US16374330

申请日：2019-04-03

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yu-Chung LIEN ,  Jiahui YUAN ,  Deepanshu DUTTA

IPC: H01L29/51 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/423 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/28

Abstract: A memory device includes a channel, a control gate electrode, and at least one charge storage element located between the channel and the control gate electrode. The control gate electrode includes a first electrically conductive layer, a second electrically conductive layer and a ferroelectric material layer located between the first electrically conductive layer and the second electrically conductive layer.

公开(公告)号：US20240237344A1

公开(公告)日：2024-07-11

申请号：US18355745

申请日：2023-07-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely SAID ,  Sarath PUTHENTHERMADAM ,  Jiahui YUAN ,  Raghuveer S. MAKALA ,  Longju LIU ,  Senaka KANAKAMEDALA

IPC: H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B43/35

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and containing a memory film and a vertical semiconductor channel; and a neighboring electrically conductive layer interference reduction feature provided for a first subset of the electrically conductive layers, such that a second subset of the electrically conductive layers lacks the neighboring electrically conductive layer interference reduction feature.

公开(公告)号：US20240105622A1

公开(公告)日：2024-03-28

申请号：US17934676

申请日：2022-09-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely SAID ,  Jiahui YUAN ,  Lito De La RAMA

IPC: H01L23/535 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582

CPC classification number: H01L23/535 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device includes a horizontal source layer which is laterally separated into laterally isolated portions located in adjacent memory blocks by a dielectric backside trench fill structure or a source isolation dielectric structure.

公开(公告)号：US20220254798A1

公开(公告)日：2022-08-11

申请号：US17351720

申请日：2021-06-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely SAID ,  Yanli ZHANG ,  Jiahui YUAN ,  Raghuveer S. MAKALA ,  Senaka KANAKAMEDALA

IPC: H01L27/11556 ,  H01L29/49

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory opening fill structures extending through the alternating stack, where each of the memory opening fill structures includes a vertical semiconductor channel, a tunneling dielectric layer, and a vertical stack of memory elements located at levels of the electrically conductive layers between a respective vertically neighboring pair of the insulating layers. Each of the memory elements is located at a level of a respective one of the electrically conductive layers between the respective vertically neighboring pair of the insulating layers. Each of the memory elements includes a first memory material portion, and a second memory material portion that is vertically spaced from the first memory material portion. The second memory material portion has a different material composition from the first memory material portion.