公开(公告)号：US10957401B2

公开(公告)日：2021-03-23

申请号：US16909832

申请日：2020-06-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kiyohiko Sakakibara ,  Ippei Yasuda ,  Ken Oowada ,  Masaaki Higashitani

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/08 ,  G11C16/24 ,  G11C16/34 ,  G11C16/04 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11519

Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.

公开(公告)号：US10950311B2

公开(公告)日：2021-03-16

申请号：US16456036

申请日：2019-06-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kiyohiko Sakakibara ,  Ippei Yasuda ,  Ken Oowada ,  Masaaki Higashitani

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C11/56 ,  G11C16/34 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11519

Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.

公开(公告)号：US11227663B2

公开(公告)日：2022-01-18

申请号：US17173023

申请日：2021-02-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kiyohiko Sakakibara ,  Ippei Yasuda ,  Ken Oowada ,  Masaaki Higashitani

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C11/56 ,  G11C16/34 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11519

Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.

公开(公告)号：US11114462B1

公开(公告)日：2021-09-07

申请号：US16794563

申请日：2020-02-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Ippei Yasuda

IPC: H01L27/11582 ,  H01L27/11565

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and a memory stack structure extending through the alternating stack. The memory stack structure includes a composite charge storage structure, a tunneling dielectric layer, and a vertical semiconductor channel. The composite charge storage structure may include a vertical stack of tubular charge storage material portions including a first charge trapping material located at levels of the electrically conductive layers, and a charge storage layer including a second charge trapping material extending through a plurality of electrically conductive layers of the electrically conductive layers. The first charge trapping material has a higher charge trap density than the second charge trapping material. Alternatively, the composite charge storage material portions may include discrete charge storage elements each containing a silicon nitride portion and a silicon carbide nitride liner.

公开(公告)号：US20210174881A1

公开(公告)日：2021-06-10

申请号：US17173023

申请日：2021-02-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kiyohiko Sakakibara ,  Ippei Yasuda ,  Ken Oowada ,  Masaaki Higashitani

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C11/56 ,  G11C16/34

Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.