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    Spacerless source contact layer replacement process and three-dimensional memory device formed by the process
    1.
    发明授权
    Spacerless source contact layer replacement process and three-dimensional memory device formed by the process 有权

    公开(公告)号：US11444101B2

    公开(公告)日：2022-09-13

    申请号：US17038870

    申请日：2020-09-30

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Jo Sato ,  Kota Funayama ,  Tatsuya Hinoue

    IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11519 ,  H01L23/522

    Abstract: A lower source-level dielectric etch-stop layer, a source-level sacrificial layer, and an upper source-level dielectric etch-stop layer are formed over a substrate. An alternating stack of insulating layers and sacrificial material layers is formed thereabove. Memory stack structures are formed through the alternating stack. Backside openings are formed through the alternating stack and into the in-process source-level material layers such that tapered surfaces are formed through the upper source-level dielectric etch-stop layer. A source cavity is formed by removing the source-level sacrificial layer, and a continuous source contact layer is formed in the source cavity and in peripheral portions of the backside openings. Portions of the continuous source contact layer overlying the tapered surfaces are removed by performing an isotropic etch process. Remaining portions of the continuous source contact layer comprise a source contact layer. The sacrificial material layers are replaced with electrically conductive layers.

    Three-dimensional memory device with a dielectric isolation spacer and methods of forming the same
    2.
    发明授权
    Three-dimensional memory device with a dielectric isolation spacer and methods of forming the same 有权

    公开(公告)号：US11152284B1

    公开(公告)日：2021-10-19

    申请号：US16868821

    申请日：2020-05-07

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Jo Sato ,  Masanori Tsutsumi ,  Hisaya Sakai

    IPC: H01L23/48 ,  H01L21/8234 ,  H01L27/11556 ,  H01L27/11582

    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures extending through the alternating stack are formed. A backside trench is formed through the alternating stack. The sacrificial material layers are replaced with electrically conductive layers. An insulating spacer and the backside contact via structure are formed within the backside trench. A dielectric isolation trench is formed by removing a peripheral portion of an upper region of the backside contact via structure and an upper portion of the insulating spacer. A dielectric isolation spacer is formed in the dielectric isolation trench to prevent an electrical short between an upper portion of the backside contact via structure and the electrically conductive layers.

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