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    Three-dimensional memory device with self-aligned multi-level drain select gate electrodes
    2.
    发明授权
    Three-dimensional memory device with self-aligned multi-level drain select gate electrodes 有权

    公开(公告)号：US10192878B1

    公开(公告)日：2019-01-29

    申请号：US15704286

    申请日：2017-09-14

    申请人： SANDISK TECHNOLOGIES LLC

    发明人： Masanori Tsutsumi ,  Shinsuke Yada ,  Yanli Zhang

    IPC分类号： H01L27/1157 ,  H01L27/11556 ,  H01L21/768 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11524

    摘要： Sacrificial memory opening fill structures are formed through an alternating stack of insulating layers and sacrificial material layers. A drain select level isolation trench extending through drain select level sacrificial material layers is formed employing a combination of a photoresist layer including a linear opening and a pair of rows of sacrificial memory opening fill structures as an etch mask. Sacrificial spacers are formed on sidewalls of the drain select level isolation trench. A drain select level isolation dielectric structure is formed in a remaining volume of the drain select level isolation trench. The sacrificial memory opening fill structures are replaced with memory stack structures. The sacrificial material layers and the sacrificial spacers are replaced with a conductive material to form electrically conductive layers and conductive connector spacers. The drain select level isolation dielectric structure is self-aligned to the memory stack structures and divides drain select level electrically conductive layers.

    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING LOW-K DRAIN-SELECT-LEVEL ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME
    6.
    发明公开
    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING LOW-K DRAIN-SELECT-LEVEL ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME 审中-公开

    公开(公告)号：US20240064985A1

    公开(公告)日：2024-02-22

    申请号：US18386456

    申请日：2023-11-02

    申请人： SANDISK TECHNOLOGIES LLC

    发明人： Masanori Tsutsumi ,  Kazuki Isozumi ,  Peng Zhang

    IPC分类号： H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27

    CPC分类号： H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27

    摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. The electrically conductive layers include word-line-level electrically conductive layers and drain-select-level electrically conductive layers overlying the word-line-level electrically conductive layers. An array of memory opening fill structures is located within an array of memory openings vertically extending through the alternating stack. An encapsulated cavity vertically extends through the drain-select-level electrically conductive layers. The array of memory opening fill structures includes two rows of first memory opening fill structures that are arranged along a first horizontal direction. Each of the first memory opening fill structures includes a respective planar straight sidewall in contact with a respective portion of a pair of straight sidewalls of the encapsulated cavity.