公开(公告)号：US20210104472A1

公开(公告)日：2021-04-08

申请号：US16594892

申请日：2019-10-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kazuma SHIMAMOTO

IPC: H01L23/00 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Memory stack structures are formed through the vertically alternating sequence. Divider trenches and slit trenches are formed such that the divider trenches laterally extend along a first horizontal direction and divide the vertically alternating sequence into a plurality of alternating stacks of insulating layers and sacrificial material layers, and the slit trenches laterally extend along a second horizontal direction that is perpendicular to the first horizontal direction. The sacrificial material layers are replaced with electrically conductive layers employing the divider trenches as a conduit for an etchant and for a reactant. Each of the divider trenches and the slit trenches are filled with material portions to provide a plurality of divider trench fill structures in the divider trenches and to provide a plurality of slit trench fill structures in the slit trenches.

公开(公告)号：US20200258876A1

公开(公告)日：2020-08-13

申请号：US16847857

申请日：2020-04-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naohiro HOSODA ,  Kazuma SHIMAMOTO ,  Tetsuya SHIRASU ,  Yuji FUKANO ,  Akio NISHIDA

IPC: H01L25/18 ,  G11C16/24 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11573 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11565 ,  G11C16/08 ,  H01L27/11529 ,  H01L27/11582 ,  G11C16/26

Abstract: A bonded assembly includes a memory die including a three-dimensional memory array located on a first single crystalline semiconductor substrate, and a logic die including a peripheral circuitry located on a second single crystalline semiconductor substrate and bonded to the memory die. The three-dimensional memory array includes word lines and bit lines. The logic die includes field effect transistors having semiconductor channels configured to flow electrical current along a channel direction that is parallel to the bit lines or word lines. Different crystallographic orientations are used for the first and second single crystalline semiconductor substrates. The crystallographic orientations of the first single crystalline semiconductor substrate are selected to minimize stress deformation of the memory chip, while the crystallographic orientations of the second single crystalline semiconductor substrate are selected to maximize device performance of the peripheral circuitry.